參數(shù)資料
型號(hào)： DS31412N
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 73/89頁(yè)
文件大?。?/td> 0K
描述： IC 12CH DS3/3 FRAMER 349-BGA
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 960mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
75 of 89
11.
AC TIMING CHARACTERISTICS
All AC timing characteristics are specified with a 50pF capacitive load on the D[7:0] and
INT pins, and a 25pF
capacitive load on all other output pins, VIH = VDD and VIL = VSS. The voltage threshold for all timing measurements
is VDD/2.
11.1 System Interface Timing
Table 11-A. Data Path Timing
(VDD = 3.3V
±5%, TA = -40°C to +85°C.) (Figure 11-1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 1)
29.0
29.1
(Note 2)
22.0
22.4
CLK Clock Period
t1
(Note 3)
19.0
19.3
ns
CLK Clock Duty Cycle
t2/t1
40
50
60
%
CLK in to DIN Setup Time
t3
(Note 4)
5.0
ns
CLK in to DIN Hold Time
t4
(Note 4)
1.0
ns
CLK in to DOUT Delay
t5
(Note 5)
2.0
12
ns
CLK out to DOUT Delay
t6
(Notes 6, 7)
2.0
8.0
ns
CLK in to CLK Out Delay
t7
(Note 8)
10
ns
Asynchronous Input High, Low Time
t8, t9
(Note 9)
200
ns
Asynchronous Input Period
t10
(Note 9)
1000
ns
Note 1: E3 mode, nongapped 34.368MHz clock.
Note 2: DS3 mode, nongapped 44.736MHz clock.
Note 3: DS3 mode, gapped 51.84MHz clock.
Note 4: TICLK input to TDAT, TOH, TOHEN, and TSOF inputs; RCLK input to RPOS and RNEG inputs.
Note 5: TICLK input to TDEN (data-enable mode) and TSOF outputs.
Note 6: ROCLK output to RDAT, RDEN (data-enable mode) and RSOF outputs; TCLK output to TPOS and TNEG outputs.
Note 7: RGCLK (gapped clock mode) output to RDAT and RSOF outputs; TDEN/TGCLK (gapped or constant clock mode) output to TSOF
output.
Note 8: TICLK input to TDEN/TGCLK (gapped clock or constant clock mode) outputs; RCLK input to ROCLK output.
Note 9: TMEI, RECU, and
RST inputs.
Table 11-B. TCCLK Data Path Timing
(VDD = 3.3V
±5%, TA = -40°C to +85°C.) (Figure 11-2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 10)
29
29.1
(Note 11)
22
22.4
TCCLK Clock Period
t1
(Note 12)
19
19.3
ns
TCCLK Clock Duty Cycle
t2/t1
40
50
60
%
TCCLK In to DIN Setup Time
t3
(Note 13)
3.0
ns
TCCLK In to DIN Hold Time
t4
(Note 13)
4.0
ns
TCCLK In to DOUT Delay
t5
(Note 14)
2.0
15
ns
TCCLK In to CLK out Delay
t7
(Note 15)
15
ns
Note 10: E3 mode, nongapped 34.368MHz clock.
Note 11: DS3 mode, nongapped 44.736MHz clock.
Note 12: DS3 mode, gapped 51.84MHz clock.
Note 13: TCCLK input to TDAT, TOH, TOHEN, and TSOF inputs.
Note 14: TCCLK input to TDEN/TGCLK (nonclock mode) and TSOF outputs.
Note 15: TCCLK input to TDEN/TGCLK (gapped clock or constant clock mode) outputs.
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