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參數(shù)資料
| 型號(hào)： | DS3131 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 173/174頁(yè) |
| 文件大?。?/td> | 1261K |
| 代理商： | DS3131 |
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DS3131
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Host Linking of Packets (Packet Chaining)
The host also has the option to link multiple packets together in a chain. Through the chain valid (CV)
bit in the packet descriptor, the host can inform the transmit DMA that the next descriptor pointer field
contains the descriptor of another HDLC packet that is ready for transmission. The transmit DMA
ignores the CV bit until it sees EOF = 1, which indicates the end of a packet. If CV = 1 when EOF = 1,
this indicates to the transmit DMA that it should use the next descriptor pointer field to find the next
packet in the chain. Figure 9-12 shows an example of packet chaining. Each column represents a separate
packet chain. In column 1, three data buffers have been linked together by the host for packet #1, and the
host has created a packet chain by setting CV = 1 in the last descriptor of packet #1.
DMA Linking of Packets (Horizontal Link Listing)
The transmit DMA also has the ability to link packets together. Internally, the transmit DMA can store
up to two packet chains, but if the host places more packet chains into the pending queue, the transmit
DMA must begin linking these chains together externally. The transmit DMA does this by writing to
packet descriptors (Figure 9-12). If columns 1 and 2 were the only two packet chains queued for
transmission, then the transmit DMA would not need to link packet chains together, but as soon as
column 3 was queued for transmission, the transmit DMA had to store the third chain externally because
it had no more room internally. The transmit DMA links the packet chain in the third column to the one
in the second column by writing the first descriptor of the third chain in the next pending descriptor
pointer field of the first descriptor of the second column (it also sets the PV bit to 1). As shown in the
figure, this chaining was carried one step farther to link the forth column to the third.
Priority Packets
The host has the option to change the order in which packets are transmitted by the DMA. If the host sets
the priority packet (PRI) bit in the pending-queue descriptor to 1, then the transmit DMA knows that this
packet is a priority packet and should be transmitted ahead of all standard packets. The rules for packet
transmission are as follows:
1) Priority packets are transmitted as soon as the current standard packet (not packet chain) finishes
transmission.
2) All priority packets are transmitted before any more standard packets are transmitted.
3) Priority packets are ordered on a first come, first served basis.
Figure 9-13 shows an example of a set of priority packets interrupting a set of standard packets. In the
example, the first priority packet chain (shown in column 2) was read by the transmit DMA from the
pending queue while it was transmitting standard packet #1. It waited until standard packet #1 was
complete and then began sending the priority packets. While column 2 was being sent, the priority
packet chains of columns 3 and 4 arrived in the pending queue, so the transmit DMA linked column four
to column three and then waited until all of the priority packets were transmitted before returning to the
standard packet chain in column 1. Note that the packet chain in column 1 was interrupted to transmit the
priority packets. In other words, the transmit DMA did not wait for the complete packet to finish
transmitting, only the current packet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3131DK | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
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