- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381725 > DS31256 (MAXIM INTEGRATED PRODUCTS INC) 256-Channel, High-Throughput HDLC Controller PDF資料下載
參數(shù)資料
| 型號： | DS31256 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 256-Channel, High-Throughput HDLC Controller |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 77/183頁 |
| 文件大?。?/td> | 1513K |
| 代理商： | DS31256 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當(dāng)前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁
DS31256 256-Channel, High-Throughput HDLC Controller
77 of 183
Bit 14/Indirect Access Read/Write (IARW).
When the host wishes to write data to set the internal receive
starting block pointer, the host should write this bit to 0. This causes the device to take data that is currently
presetn in the RFSBP register and write it to the channel location indicated by the HCID bits. When the device
completes the write, the IAB is set to 0.
Bit 15/Indirect Access Busy (IAB).
When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the
write operation completes.
Register Name:
RFSBP
Register Description:
Receive FIFO Starting Block Pointer
Register Address:
0904h
Bit #
7
6
5
4
Name
RSBP7
RSBP6
RSBP5
RSBP4
Default
Bit #
15
14
13
12
Name
n/a
n/a
n/a
n/a
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 9/Starting Block Pointer (RSBP0 to RSBP9).
These bits determine which of the 1024 blocks within the
receive FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of
the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits
are read, they report the current block pointer being used to write data into the receive FIFO from the HDLC Layer
2 engines.
0000000000 (000h) = use block 0 as the starting block
0111111111 (1FFh) = use block 511 as the starting block
1111111111 (3FFh) = use block 1023 as the starting block
Register Name:
RFBPIS
Register Description:
Receive FIFO Block Pointer Indirect Select
Register Address:
0910h
Bit #
7
6
5
4
Name
BLKID7
BLKID6
BLKID5
BLKID4
Default
0
0
0
0
Bit #
15
14
13
12
Name
IAB
IARW
n/a
n/a
Default
0
0
0
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 9/Block ID (BLKID0 to BLKID9)
0000000000 (000h) = block number 0
0111111111 (1FFh) = block number 511
1111111111 (3FFh) = block number 1023
Bit 14/Indirect Access Read/Write (IARW).
When the host wishes to read data from the internal receive block
pointer RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the block
location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be
read from the RFBP register, the IAB bit is set to 0. When the host wishes to write data to the internal receive
3
2
1
0
RSBP3
11
n/a
RSBP2
10
n/a
RSBP1
9
RSBP9
RSBP0
8
RSBP8
3
2
1
0
BLKID3
0
11
n/a
0
BLKID2
0
10
n/a
0
BLKID1
0
9
BLKID9
0
BLKID0
0
8
BLKID8
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3146 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3148 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS31412 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS31412N | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3146N | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31256+ | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256B | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。