參數(shù)資料
型號(hào)： DS26518G
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 數(shù)字傳輸電路
英文描述： 8-Port T1/E1/J1 Transceiver
中文描述： DATACOM, FRAMER, BGA256
封裝： 17 X 17 MM, 1 MM, PITCH, CSBGA-256
文件頁(yè)數(shù)： 34/286頁(yè)
文件大?。?/td> 1539K
代理商： DS26518G
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DS26518 8-Port T1/E1/J1 Transceiver
34 of 286
9.4
Initialization and Configuration
9.4.1 Example Device Initialization and Sequence
STEP 1: Reset the device by pulling the
RESETB
pin low, applying power to the device, or by using the software
reset bits outlined in Section
9.2.2
. Clear all reset bits. Allow time for the reset recovery.
STEP 2: Check the Device ID in the
IDR
register.
STEP 3: Write the
GTCCR1
register to correctly configure the system clocks. If supplying a 1.544MHz MCLK
follows this write with at least a 300ns delay in order to allow the clock system to properly adjust.
STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register
locations.
STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the
TMMR
and
RMMR
registers for each framer. Set the FRM_EN bit to 1 in the
TMMR
and
RMMR
registers. If using software transmit
signaling in E1 mode, program the
E1TAF
and
E1TNAF
registers as required. Configure the framer Transmit
Control Registers (
TCR1
–
TCR4
). Configure the framer Receive Control Registers (
RCR1
–
RCR3
). Configure other
framer features as appropriate.
STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the
LTRCR
register.
Configure the line build-out for each LIU. Configure other LIU features as appropriate. Set the TE (transmit enable)
bit to turn on the TTIPn and TRINGn outputs.
STEP 7: Configure the elastic stores, HDLC controller, and BERT as needed.
STEP 8: Set the INIT_DONE bit in the
TMMR
and
RMMR
registers for each framer.
9.5
Global Resources
All eight framers share a common microprocessor port and a common MCLK. There is a common software
configurable BPCLK1 output. A set of global registers includes global resets, global interrupt status, interrupt
masking, clock configuration, and the device ID register. See the global register bit map in
Table 10-6
. A common
JTAG controller is used for all ports.
9.6
Per-Port Resources
Each port has an associated framer, LIU, BERT, jitter attenuator, and transmit/receive HDLC controller. Each of the
per-port functions has its own register space.
9.7
Device Interrupts
Figure 9-10
diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers
GFISR1
,
GLISR1
, and
GBISR1
to quickly identify which of the eight transceivers is
(are) causing the interrupt(s). The host can then read the specific transceiver’s interrupt information registers (
TIIR
,
RIIR
) and the latched status registers (
LLSR
,
BLSR
) to further identify the source of the interrupt(s). If TIIR or RIIR
is the source, the host reads the transmit latched status or the receive latched status registers for the source of the
interrupt. All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been
serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status
register. All latched status bits must be cleared by the host writing a “1” to the bit location of the interrupt condition
that has been serviced. Latched status bits that have been masked via the interrupt mask registers are masked
from the interrupt information registers. The interrupt mask register bits prevent individual latched status conditions
from generating an interrupt, but they do not prevent the latched status bits from being set. Therefore, when
servicing interrupts, the user should XOR the latched status with the associated interrupt mask in order to exclude
bits for which the user wished to prevent interrupt service. This architecture allows the application host to
periodically poll the latched status bits for noninterrupt conditions, while using only one set of registers.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26518G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26518GA2+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26518GN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26518GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26518GNA2+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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