參數(shù)資料
型號: DS26503L+
廠商: Maxim Integrated Products
文件頁數(shù): 53/122頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
36 of 122
Bits 4 to 7: Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit path for the
DS26503.
TMODE3
TMODE2
TMODE1
TMODE0
Transmit Path Operating Mode
0
T1 D4
0
1
T1 ESF (Note: In this mode the TFSE (T1TCR2.6) bit should be
set = 0.)
0
1
0
J1 D4
0
1
J1 ESF
0
1
0
E1 FAS
0
1
0
E1 FAS + CAS (Note 1)
0
1
0
1
Reserved
0
1
0
E1 CRC4
0
1
0
E1 CRC4 + CAS (Note 1)
0
1
Reserved
1
0
E1 G.703 2048 kHz Synchronization Interface
1
0
1
Reserved
1
0
1
0
Reserved
1
0
1
6312kHz Synchronization Interface (Note 2)
1
0
Reserved
1
0
1
Reserved
Note 1:
The DS26503 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the
multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame
aligned to sync signal on the TS pin.
Note 2:
In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be configured to
transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7)
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