參數(shù)資料
型號(hào)： DS26303L-75
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 數(shù)字傳輸電路
英文描述： 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
中文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, MS-026, LQFP-144
文件頁(yè)數(shù)： 58/97頁(yè)
文件大?。?/td> 966K
代理商： DS26303L-75
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
58 of 97
6.3.3 Dual-Rail Mode
Dual-rail mode consists of TPOS, TNEG, and TCLK pins on the system side. NRZ data is sampled on the falling
edge of TCLK as shown in
Figure 10-12
. The zero substitution B8ZS or HDB3 is not allowed. The TPOS/TNEG
data is encoded in AMI format on the TTIP and TRING pins. The data that appears on the TPOS pin is output on
TTIP and data on the TRING is output on TRING after pulse shaping. The single-rail-select register (
SRMS)
is
used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS and TNEG can be overwritten
in the maintenance mode by setting the BERT Control Register (
BTCR
).
6.3.4 Single-Rail Mode
Single-rail mode consists of TPOS, TNEG, and TCLK pins on the system side. NRZ data is sampled on the falling
edge of TCLK as shown in
Figure 10-12
. The zero substitution B8ZS or HDB3 is allowed. The TPOS data is
encoded in AMI format on the TTIP and TRING pins after pulse shaping. The single-rail-mode select (
SRMS)
is
used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS can be overwritten in the
maintenance mode by setting in BERT control register (
BTCR
).
6.3.5 Zero Suppression—B8ZS or HDB3
B8ZS coding is available when the device is in T1 mode selected by the TS2, TS1, and TS0 bits in the
TS
register.
Setting the LCS bit in the
LCS
register enables B8ZS. Note that if the individual LIU is configured in E1 mode, then
HDB3 code substitution can be selected. Bipolar violations can be inserted via the TNEG/BPVI pin or transmit
maintenance register settings only if B8ZS or HDB3 coding is turned off. B8ZS substitution is defined in ANSI
T1.102 and HDB3 in ITUT G.703 standards.
6.3.6 Transmit Power-Down
The transmitter is powered down if the relevant bits in the
TPDE
register are set.
6.3.7 Transmit All Ones
When transmit all ones is invoked, continuous 1s are transmitted using MCLK as the timing reference. Data input at
TPOS and TNEG is ignored. Transmit all ones can be sent by setting bits in the
TAOE
register. Transmit all ones
are enabled if bits in register
ATAOS
are set and the corresponding receiver goes into an LOS state in the status
register
LOSS.
6.3.8 Drive Failure Monitor
The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a Short Circuit on the Secondary
side of the Transmit Transformer. The drive current will be limited to 50 ma if a short circuit is detected. The
DFMS
status registers and the corresponding Interrupt and Enable Registers can be used to monitor the driver failure.
6.4 Receiver
The DS26303’s eight receivers are all identical. A 2:1 transformer steps down the input from the line. The DS26303
is designed to be fully software-selectable for E1 and T1/J1 without the need to change any external resistors for
the receive side. The output of the internal termination circuitry is fed into a peak detector.
The peak detector and data slicer process the received signal. The output of the data slicer goes to clock and data
recovery. A 2.048/1.544 PLL is internally multiplied by 8 by another internal PLL and fed to the clock recovery
system derives E1 or T1 clock. The clock-recovery system uses the clock from the PLL circuit to form an 8-times
oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding
performance to meet jitter tolerance specifications. Depending on selection options, B8ZS/HDB3/AMI decoding is
performed. These decoded data is provided to the system side in either single-rail or dual-rail mode. The selection
of single rail or dual rail is done by settings in the
SRMS
register.
6.4.1 Peak Detector and Slicer
The slicer determines the polarity and presence of the received data. The output of the slicer is sent to the clock
and data recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for determination
of the slicing threshold.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303L-75+ 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-75+A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-75A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-120 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-120+ 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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