參數(shù)資料
型號(hào): DS2432P/T&R
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Programmable ROM
英文描述: 1K X 1 1-WIRE SERIAL EEPROM, PDSO6
封裝: 0.150 INCH, TSOC-6
文件頁(yè)數(shù): 6/16頁(yè)
文件大?。?/td> 168K
代理商: DS2432P/T&R
Abridged Data Sheet
DS2432
14 of 14
AC ELECTRICAL CHARACTERISTICS
OVERDRIVE SPEED
(VPUP=2.8V to 5.25V; -40°C to +85°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Time Slot
tSLOT
6
16
s
Write 1 Low Time
tLOW1
1
2
s
Write 0 Low Time
tLOW0
6
16
s
Read Low Time
tLOWR
1
2
s
Read Data Valid
tRDV
2
s
10
Release Time
tRELEASE
0
1.5
4
s
Read Data Setup
tSU
1
s
4
Recovery Time
tREC
1
s
Reset High Time
tRSTH
48
s
Reset Low Time
tRSTL
48
80
s
Presence Detect High
tPDHIGH
2
6
s
Presence Detect Low
tPDLOW
8
24
s
Programming Time
tPROG
10
ms
SHA Computation Time
tCSHA
See full version of data sheet.
NOTES:
1. All voltages are referenced to ground.
2. VPUP = external pull-up voltage.
3. Input load is to ground.
4. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 s of this falling edge.
5. Capacitance on the data pin could be 800 pF when power is first applied. If a 5 k
Ω resistor is used to
pull up the data line to VPUP, 5 s after power has been applied the parasite capacitance will not affect
normal communications.
6. The reset low time (tRSTL) should be restricted to a maximum of 960 s, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
7. VIH is a function of the external pull-up resistor and VPUP.
8. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse. VIL is a function of VPUP and the reset low time.
9. During write operations to the EEPROM the voltage on the 1-Wire bus must not fall below 2.8V. The
EEPROM write cycle takes max. 10 ms.
10. The optimal sampling point for the master is as close as possible to the end time of the tRDV period
without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of time for
the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures that a read
will occur before the fastest 1-Wire device releases the line (tRELEASE = 0).
相關(guān)PDF資料
PDF描述
DS2432X 1K X 1 1-WIRE SERIAL EEPROM, PBGA6
DS2432P 1K X 1 1-WIRE SERIAL EEPROM, PDSO6
DS2433 512 X 8 1-WIRE SERIAL EEPROM, PBCY3
DS2433X 4K X 1 1-WIRE SERIAL EEPROM, UUC2
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