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參數(shù)資料
| 型號： | DS2413Q+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 2CH ADDRESS 6-TDFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 系列： | * |
DS2413: 1-Wire Dual Channel Addressable Switch
3 of 18
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Standard speed, VPUP > 4.5V
67.4
75
Standard speed
69.6
75
Overdrive speed, VPUP 4.5V
7.7
10
Presence Detect Sample
Time (Notes 1, 20)
tMSP
Overdrive speed
9.1
10
s
IO PIN, 1-Wire WRITE
Standard speed, VPUP > 4.5V
60
120
Standard speed (Note 14)
62
120
Overdrive speed, VPUP 4.5V
(Note 14)
7
16
Write-0 Low Time
(Notes 1, 17)
tW0L
Overdrive speed (Note 14)
8
16
s
Standard speed
5
15
Write-1 Low Time
(Notes 1, 17)
tW1L
Overdrive speed
1
2
s
IO PIN, 1-Wire READ
Standard speed
5
15 -
Read Low Time
(Notes 1, 18)
tRL
Overdrive speed
1
2 -
s
Standard speed
tRL +
15
Read Sample Time
(Notes 1, 18)
tMSR
Overdrive speed
tRL +
2
s
PIO Pins
Leakage Current
ILP
Pin at 28V (Note 19)
8.5
24
A
Input Capacitance
CP
(Note 5)
100
pF
Output low voltage
VOLP
20mA load current
0.4
V
Input Low Voltage
VILP
(Note 1)
0.8
V
Input High Voltage
(Note 21)
VIHP
(Note 1)
VPUP –
0.3V
28
V
Note 1:
System requirement.
Note 2:
Full RPUP range guaranteed by design and simulation. not production tested. Production testing performed at a fixed RPUP value.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00 or DS2480B may be required. The DS2482-x00 may not
always detect the DS2413 presence pulse. For proper operation it may be necessary to disregard (force to 1) the PPD bit in the
DS2482-x00 status register.
Note 3:
The I-V characteristic is linear for voltages greater than 10V.
Note 4:
Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2k resistor is used to pull up the data line, 2.5s
after VPUP has been applied the parasite capacitance will not affect normal communications.
Note 5:
Guaranteed by design and simulation. Not production tested.
Note 6:
The voltage on IO needs to be less than or equal to VILMAX whenever the master drives the line low.
Note 7:
VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire Recovery Times. The VTH and
VTL maximum specifications are valid at VPUPmax (5.25V). In any case, VTL < VTH < VPUP.
Note 8:
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 9:
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10:
After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.
Note 11:
The I-V characteristic is linear for voltages less than 1V.
Note 12:
Applies to a single DS2413 attached to a 1-Wire line.
Note 13:
The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 14:
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
Note 15:
tPDH is deemed to have ended when the voltage on IO drops below 80% of VPUP on the leading edge of the presence-detect low
pulse. tPDL is deemed to have begun when the voltage on IO drops below 20% of VPUP on the leading edge of the pulse.
Note 16:
Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of VPUP and the time at which the voltage is 20% of VPUP.
Note 17:
in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum
duration for the master to pull the line low is tW1Lmax + tF - and tW0Lmax + tF - respectively.
Note 18:
in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is tRLmax + tF.
Note 19:
The I-V characteristic is linear for voltages greater than 7V.
Note 20:
tMSP is a system required sample point and not directly production tested. Production testing is performed on related parameters
tPDH and tPDL. Parameter tFPD is guaranteed by design and simulation, not production tested.
Note 21:
Production tested for VIHP(min). VIHP(max) is guaranteed by design and simulation, not production tested.
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