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參數(shù)資料
型號(hào): DS2404B
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 24/29頁(yè)
文件大?。?/td> 0K
描述: IC ECONORAM TIMECHIP 5.5V 16SSOP
標(biāo)準(zhǔn)包裝: 77
系列: EconoRAM
類型: 二進(jìn)制計(jì)數(shù)器
特點(diǎn): 警報(bào)器,方波輸出
時(shí)間格式: 二進(jìn)制
數(shù)據(jù)格式: 二進(jìn)制
接口: 1 線和 3 線
電源電壓: 2.8 V ~ 5.5 V
電壓 - 電源,電池: 2.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
DS2404
4 of 29
Port selection is accomplished on a first-come, first-serve basis. Whichever port comes out of reset first
will obtain control. For the 3-wire port, this is done by bringing RST high. For the 1-Wire port, this is
done on the first falling edge of I/O after the reset and presence pulses. (See “1-Wire Signaling” section.)
More information on how to arbitrate port access is found in section “Device Operation Modes” later in
this document.
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power
whenever the I/O, RST , or VCC pins are high. When using the 1-Wire port in battery operate mode,
RST
and VCC provide no power since they are low. However, I/O will provide sufficient power as long as
the specified timing and voltage requirements are met. The advantages of parasite power are two-fold:
1) by parasiting off these pins, battery power is conserved and 2) the ROM may be read in absence of
normal power. For instance, in battery-operate mode, if the battery fails, the ROM may still be read
normally.
In battery-backed mode, if VCC fails, the port switches in the battery but inhibits communication. The
ROM may still be read normally over the 1-Wire port if RST is low.
64-BIT LASERED ROM
Each DS2404 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code (DS2404 code is 04h). The next 48 bits are a unique serial number. The last eight bits are a CRC of
the first 56 bits. (See Figure 2.)
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas
1-Wire Cyclic Redundancy Check is available in Application Note 27, “Understanding and Using Cyclic
Redundancy Checks with Dallas Semiconductor iButton Products”.
The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number
is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the eight bits of CRC should return the shift register to all zeros.
64-BIT LASERED ROM Figure 2
CRC
SERIAL NUMBER
DS2404 FAMILY CODE
8 BITS
48-BIT UNQUE NUMBER
04h
MSB
LSB
1-WIRE CRC CODE Figure 3
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