20. The reset low time (tRSTL) should be restric" />
參數(shù)資料
型號(hào): DS2404B
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 22/29頁(yè)
文件大?。?/td> 0K
描述: IC ECONORAM TIMECHIP 5.5V 16SSOP
標(biāo)準(zhǔn)包裝: 77
系列: EconoRAM
類型: 二進(jìn)制計(jì)數(shù)器
特點(diǎn): 警報(bào)器,方波輸出
時(shí)間格式: 二進(jìn)制
數(shù)據(jù)格式: 二進(jìn)制
接口: 1 線和 3 線
電源電壓: 2.8 V ~ 5.5 V
電壓 - 電源,電池: 2.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
DS2404
29 of 29
20. The reset low time (tRSTL) should be restricted to a maximum of 960μs, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
21. When the battery is attached, the oscillator powers up in the off state.
22. The optimal sampling point for the master is as close as possible to the end time of the 15
μs tRDV
period without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of
time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures
that a read will occur before the fastest 1-Wire device(s) release the line (tRELEASE = 0).
23. The duration of the low pulse sent by the master should be a minimum of 1μs with a minimum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write 1 Low Time or before the master samples in the case of
a Read Low Time.
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