480s ≤ tRSTL< ∞" />
參數(shù)資料
型號(hào): DS2401Z+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 9/11頁
文件大?。?/td> 0K
描述: IC SILICON SERIAL NUMBER SOT223
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
其它名稱: DS2401Z+T&RDKR
DS2401
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
480s ≤ tRSTL< ∞ *
480s ≤ tRSTH< ∞ (includes recovery time)
15s ≤ tPDH < 60s
60s ≤ tPDL< 240s
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960s.
READ/WRITE TIMING DIAGRAM Figure 6
Write-One Time Slot
60s ≤ tSLOT < 120s
1s ≤ tLOW1< 15s
1s ≤ tREC< ∞
RESISTOR
MASTER
RESISTOR
MASTER
DS2401
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