參數(shù)資料
型號(hào)： DS229SN
廠商： DALLAS SEMICONDUCTOR
元件分類： Line Driver or Receiver
英文描述： LINE TRANSCEIVER, PDSO20
封裝： SOIC-20
文件頁(yè)數(shù)： 7/47頁(yè)
文件大小： 413K
代理商： DS229SN
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
15
Maxim Integrated
Single-ended inputs can be converted by either channel
1 or 2 by initiating a conversion on the appropriate chan-
nel with the SE[3:0] bits set to the desired single-ended
input (Table 7). Several of the single-ended signals are
converted with a fixed gain. The reduced gain of 0.7V/V
allows signals at or near the supply rails to be converted
without concern of saturation. Other single-ended signals
can be converted with the full selectable PGA gain range.
Programmable-Gain Amplifier
The gain of the differential inputs and several
single-ended inputs can be set to values between
0.99V/V to 244V/V as shown in Table 14. The PGA bits
are set in ADC_Config_nA where n = 1, 2, or T. The gain
setting must be selected prior to initiating a conversion.
ADC Conversion Time and Resolution
The ADC conversion time is a function of the selected
resolution, ADC clock (fADC), and system clock frequen-
cy (fCLK). The resolution can be selected from 9 bits to 16
bits in the ADC_Config_nA (where n = 1, 2, or T) register
by bits RESn[2:0]. The lower resolution settings (9 bit)
convert faster than the higher resolution settings (16 bit).
The ADC clock fADC is derived from the primary system
clock fCLK by a prescalar divisor. The divisor can be set
from 4 to 512, producing a range of fADC from 1MHz
down to 7.8125kHz when fCLK is operating at 4.0MHz.
Other values of fCLK produce other scaled values of
fADC. See Tables 15 and 16.
Systems operating with very low power consumption
benefit from the reduced fADC clock rate. Slower clock
speeds require less operating current. Systems operat-
ing from a larger power consumption budget can use
the highest fADC clock rate to improve speed perfor-
mance over power performance.
The ADC conversion times for various resolution and
clock-rate settings are summarized in Table 17. The
conversion time is calculated by the formula:
tCONVERT = (no. of fADC clocks per conversion) /
fADC
INP1
INM1
INP2
INM2
CO
DAC
REF
TEMPERATURE
SENSOR
VBG
VDD
4 x VBG
2 x VREF
ADC
INMn
VBG
OUTnSM
OUTnLG
VDD
VSS
DACnOUT VIA OUTnSM
INPn
1
2
3
4
5
6
7
8
9
NO.
SINGLE-ENDED
DACnOUT VIA OUTnLG
00h
ADC_Control
08h
ADC_Config_TA
07h
ADC_Data_T
06h
ADC_Config_2B
09h
ADC_Config_TB
02h
ADC_Config_1A
05h
ADC_Config_2A
04h
ADC_Data_2
03h
01h
ADC_Data_1
ADC_Config_1B
PGA
VSS
M
U
X
Figure 4. ADC Module
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