參數(shù)資料
型號： DS229SN
廠商： DALLAS SEMICONDUCTOR
元件分類： Line Driver or Receiver
英文描述： LINE TRANSCEIVER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 43/47頁
文件大?。?/td> 413K
代理商： DS229SN
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
5
Maxim Integrated
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LARGE OP AMP
Input Offset Voltage
VOS_LG
0±6
mV
Input Bias Current
IB_LG
±225
nA
DC Gain
AVOL_LG
OUTnLG = 0.5V to 4.5V (n = 1 or 2),
RLOAD =
∞
100
dB
Gain Bandwidth Product
GBW_LG
AVOL_LG = +1V/V
4.0
MHz
Slew Rate
SR_LG
AVOL_LG = +1V/V
3.2
V/s
Common-Mode Input Range
CMR_LG
VSS + 0.02
VDD - 0.02
V
Common-Mode Rejection Ratio
CMRR_LG
VCM OPAMP = VSS to VDD
70
dB
Power-Supply Rejection Ratio
PSRR_LG
At DC
70
dB
0.1Hz to 1kHz
19
Input-Referred Noise Voltage
VN_LG
0.1Hz to 1MHz
160
VRMS
RLOAD =
∞
VDD - 0.1
Output-Voltage High
VOH_LG
RLOAD = 1k
Ω to VSS
VDD - 0.125
V
RLOAD =
∞
0.03
Output-Voltage Low
VOL_LG
RLOAD = 1k
Ω to VDD
0.13
V
Output Source Current
ISRC_LG
VOUTnLG = VOH_LG, RLOAD = 1k
Ω to VSS
-4.9
mA
Output Sink Current
ISNK_LG
VOUTnLG = VOL_LG, RLOAD = 1k
Ω to VDD
4.9
mA
Maximum Output Load
Capacitance
CL_LG
RLOAD =
∞, phase margin > 55°
200
pF
OP-AMP SWITCH
Analog Signal Range
VSW
VSS
VDD
V
On-Resistance
RON
5k
Ω
Off-Isolation
VISO
80
dB
DIGITAL-TO-ANALOG CONVERTER
Resolution
RESDAC
16
Bits
Integral Nonlinearity
INLDAC
3
Bits
Differential Nonlinearity
DNLDAC
±1
Bits
Offset Error
VDAC OS
DAC ref = VDD, DAC data = 0000h
VDD / 2
- 0.06
VDD / 2
+ 0.06
V
Bit Weight
BWDAC
DAC ref = 5VDC
91.55
V/LSB
Power-Supply Rejection
PSRDAC
At DC, DAC ref = VREF
0.02
%FS
Output Noise
ONDAC
DAC buffer is the small op amp
±3
LSB
Output Settling Time
STDAC
To 0.1% of final value
250
s
PULSE-WIDTH MODULATOR
Resolution
RESPWM
(Note 6)
12
Bits
Period
PPWM
fCLK = 4.0MHz
8.192
ms
ELECTRICAL CHARACTERISTICS (continued)
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF = VSS = 0V,
TA = +25°C, unless otherwise noted.) (Note 1)
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