參數(shù)資料
型號： DS21Q58L
廠商： Maxim Integrated Products
文件頁數(shù)： 30/74頁
文件大?。?/td> 0K
描述： IC TXRX E1 QUAD 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 90
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 230mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠(yuǎn)程檢測器和發(fā)生器
DS21Q58 E1 Quad Transceiver
36 of 74
11.
SIGNALING OPERATION
Registers SA1 and SA16 are used to access the transmit and receive signaling function. Normally, reading these
registers accesses the receive signaling data and writing these registers sources signaling data for the transmitter.
The user can read what was written to the transmit signaling buffer by setting CCR6.5 = 1, then reading
SA1–SA16. In most applications, however, CCR6.5 should be set = 0.
11.1 Receive Signaling
Signaling data is sampled from time slot 16 in the receive data stream and copied into the receive signaling buffers.
The host can access the signaling data by reading SA1 through SA16. The signaling information in these registers
is always updated on multiframe boundaries. The SR2.7 bit in status register 2 can be used to alert the host that
new signaling data is present in the receive signaling buffers. The host has 2ms to read the signaling buffers before
they are updated.
11.2 Transmit Signaling
Insertion of signaling data from the transmit signaling buffers is enabled by setting CCR6.3 = 1. Signaling data is
loaded into the transmit signaling buffers by writing the signaling data to SA1–SA16. On multiframe boundaries, the
contents of the transmit signaling buffer is loaded into a shift register for placement in the appropriate bit position in
the outgoing data stream. The user can use the transmit multiframe interrupt in status register 2 (SR2.5) to know
when to update the signaling bits. The host has 2ms to update the signaling data. The user only needs to update
the signaling data that has changed since the last update.
11.3 CAS Operation
For CAS mode, the user must provide the CAS alignment pattern (four 0s in the upper nibble of TS16). Typically
this is done by setting the upper four bits of SA1 = 0. The lower four bits are alarm bits. The user only needs to
update the appropriate channel associated signaling data in SA2–SA16 on multiframe boundaries.
Register Name:
SA1 to SA16
Register Description:
Signaling Registers
Register Address:
30h to 3Fh
(MSB)
(LSB)
0
X
Y
X
SA1
CH1-A
CH1-B
CH1-C
CH1-D
CH16-A
CH16-B
CH16-C
CH16-D
SA2
CH2-A
CH2-B
CH2-C
CH2-D
CH17-A
CH17-B
CH17-C
CH17-D
SA3
CH3-A
CH3-B
CH3-C
CH3-D
CH18-A
CH18-B
CH18-C
CH18-D
SA4
CH4-A
CH4-B
CH4-C
CH4-D
CH19-A
CH19-B
CH19-C
CH19-D
SA5
CH5-A
CH5-B
CH5-C
CH5-D
CH20-A
CH20-B
CH20-C
CH20-D
SA6
CH6-A
CH6-B
CH6-C
CH6-D
CH21-A
CH21-B
CH21-C
CH21-D
SA7
CH7-A
CH7-B
CH7-C
CH7-D
CH22-A
CH22-B
CH22-C
CH22-D
SA8
CH8-A
CH8-B
CH8-C
CH8-D
CH23-A
CH23-B
CH23-C
CH23-D
SA9
CH9-A
CH9-B
CH9-C
CH9-D
CH24-A
CH24-B
CH24-C
CH24-D
SA10
CH10-A
CH10-B
CH10-C
CH10-D
CH25-A
CH25-B
CH25-C
CH25-D
SA11
CH11-A
CH11-B
CH11-C
CH11-D
CH26-A
CH26-B
CH26-C
CH26-D
SA12
CH12-A
CH12-B
CH12-C
CH12-D
CH27-A
CH27-B
CH27-C
CH27-D
SA13
CH13-A
CH13-B
CH13-C
CH13-D
CH28-A
CH28-B
CH28-C
CH28-D
SA14
CH14-A
CH14-B
CH14-C
CH14-D
CH29-A
CH29-B
CH29-C
CH29-D
SA15
CH15-A
CH15-B
CH15-C
CH15-D
CH30-A
CH30-B
CH30-C
CH30-D
SA16
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