參數(shù)資料
型號(hào): DS21Q348
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PBGA144
封裝: BGA-144
文件頁數(shù): 24/67頁
文件大?。?/td> 339K
代理商: DS21Q348
DS21348/Q348
30 of 67
Table 7-1 RECEIVED ALARM CRITERIA
ALARM
E1/T1
SET CRITERIA
CLEAR CRITERIA
RUA1
E1
Less than 2 zeros in 2 frames
(512 bits)
More than 2 zeros in 2 frames
(512 bits)
RUA1
T1
Over a 3 ms window, 5 or less
zeros are received
Over a 3 ms window, 6 or more
zeros are received
RCL
1
E1
255 (or 2048)
2 consecutive zeros
received
(G.775)
In 255 bit times, at least 32 ones
are received
RCL
1
T1
192 (or 1544)
2 consecutive zeros
are received
14 or more ones out of 112
possible bit positions are
received starting with the first
one received
Note 1: Receive carrier loss (RCL) is also known as loss of signal (LOS) or Red Alarm in T1.
Note 2: See CCR1.5 for details.
SR (06H): STATUS REGISTER
(MSB)
(LSB)
LUP
LDN
LOTC
RUA1
RCL
TCLE
TOCD
PRBSD
SYMBOL
POSITION
NAME AND DESCRIPTION
LUP
(latched)
SR.7
Loop Up Code Detected. Set when the loop up code defined
in registers RUPCD1 and RUPCD2 is being received. See
Section 6 for details.
LDN
(latched)
SR.6
Loop Down Code Detected. Set when the loop down code
defined in registers RDNCD1 and RDNCD2 is being received.
See Section 6 for details.
LOTC
(real time)
SR.5
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for 5
sec (±2sec). Will force the LOTC pin high.
RUA1
(latched)
SR.4
Receive Unframed All Ones. Set when an unframed all ones
code is received at RRING and RTIP. See Table 7-1for details.
RCL
(latched)
SR.3
Receive Carrier Loss. Set when a receive carrier loss
condition exists at RRING and RTIP. See Table 7-1for details.
TCLE
(real time)
SR.2
Transmit Current Limit Exceeded. Set when the 50 mA
(rms) current limiter is activated whether the current limiter is
enabled or not.
TOCD
(real time)
SR.1
Transmit Open Circuit Detect. Set when the device detects
that the TTIP and TRING outputs are open circuited.
PRBSD
(real time)
SR.0
PRBS Detect. Set when the receive-side detects a 2
15-1 (E1) or
a 2
20-1 (T1) Pseudo Random Bit Sequence (PRBS).
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