- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1914 > DS21FF44 (Maxim Integrated Products)IC FRAMER E1 4X4 16CH 300-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | DS21FF44 |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 73/117頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER E1 4X4 16CH 300-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | E1 調(diào)幀器 |
| 接口： | 并行/串行 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 300mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 300-BBGA |
| 供應(yīng)商設(shè)備封裝： | 300-PBGA（27x27） |
| 包裝： | 管件 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)當(dāng)前第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
DS21FT44/DS21FF44
59 of 117
14.2. Hardware-Based Signaling
Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in
a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode is always enabled.
In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled,
then the backplane clock (RSYSCLK) must be 2.048 MHz. The ABCD signaling bits are output on
RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (2 ms) unless a
freeze is in effect. See the timing diagrams in Section 22 for some examples.
The other hardware based signaling operating mode called signaling re–insertion can be invoked by
setting the RSRE control bit high (CCR3.3=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data be re–aligned at the RSER output according to this applied
multiframe boundary in this mode, the elastic store must be enabled the backplane clock must be 2.048
MHz.
The signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE
control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit
(CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization,
carrier loss, or slip has occurred.
The 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the
RSIG pin (and at the RSER pin if RSRE=1 by CCR3.3). When freezing is enabled (RFE=1), the
signaling data will be held in the last known good state until the corrupting error condition subsides.
When the error condition sub-sides, the signaling data will be held in the old state for an additional 3 ms
to 5 ms before being allowed to be updated with new signaling data.
Transmit Side
By the THSE control bit (CCR3.2), the DS21Q44 can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
hardware signaling insertion capabilities of each framer are available whether the transmit side elastic
store is enabled or disabled. If the transmit side elastic store is enabled, the backplane clock (TSYSCLK)
must be 2.048 MHz.
When hardware signaling insertion is enabled on a framer (THSE=1), then the user must enable the
Transmit Channel Blocking Register Function Select (TCBFS) control bit (CCR3.6=1). This is needed so
that the CAS multiframe alignment word, multiframe remote alarm, and spare bits can be added to
timeslot 16 in frame 0 of the multiframe. The TS1 register should be programmed with the proper
information. If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from
TSER (or TSIG if CCR3.2=1) and a one implies that signaling data for that channel is to be sourced from
the Transmit Signaling (TS) registers. See definition below.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21FT44N+ | IC FRAMER 4X4 16CH 300-BGA |
| DS21Q352B | IC TXRX QUAD T1/E1 3.3V 256-BGA |
| DS21Q41BT | IC FRAMER T1 QUAD 128-TQFP |
| DS21Q42T+ | IC FRAMER ENHANCED T1 4X 128TQFP |
| DS21Q43-ATN | IC FRAMER E1 QUAD 5V 128-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FF44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT40 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Four x Three 12 Channel E1 Framer |
| DS21FT40N | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21FT42 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT42N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。