- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97867 > DS2182A (DALLAS SEMICONDUCTOR) DATACOM, FRAMER, PDIP28 PDF資料下載
參數(shù)資料
| 型號(hào)： | DS2182A |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PDIP28 |
| 封裝： | 0.600 INCH, DIP-28 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 270K |
| 代理商： | DS2182A |
DS2182A
14 of 25
is established using the FT information, while multiframe sync is established only if valid FS information
is present. If no valid FS pattern is identified, the synchronizer moves to the FT alignment, RLOS goes
low, and a false multiframe position may be indicated by RMSYNC. RFER indicates when the received
S-bit pattern does not match the assumed internal multiframe alignment. This mode will be used in
applications where non-standard S-bit patterns exist. In such applications, multiframe alignment
information can be decoded externally by using the S-bits present at RLINK.
SYNC TIME (RCR1.2)
Bit RCR1.2 determines the number of consecutive framing pattern bits to be qualified before SYNC is
declared. If RCR1.2 =1, the algorithm validates 24 bits; if RCR1.2 = 0, 10 bits are validated. Validating
24 bits results in superior false framing protection while 10-bit testing minimizes reframe time. In either
case, the synchronizer only establishes resync when one and only one candidate is found (see Table 5).
AVERAGE REFRAME TIME Table 5
RCR1.2=0
RCR1.2=1
FRAME
MODE
MIN
AVG.
MAX.
MIN.
AVG.
MAX
193S
3.0ms
3.75ms
4.5ms
6.5ms
7.25ms
8.0ms
193E
6.0ms
7.5ms
9.0ms
13.0ms
14.5ms
16.0ms
NOTE:
1. Average reframe time is defined here as the average time it takes from the start of resync (rising edge
of RLOS) to the actual loading of the new alignment (on a multiframe edge) into the output receive
timing.
SYNC ENABLE (RCR1.1)
When RCR1.1 is cleared, the receiver initiates automatic resync if an OOF event occurs or if carrier loss
(192 consecutive 0s) occurs (depends on RCR1.7). When RCR1.1 is set, the automatic resync circuitry is
disabled. In this case, resync can only be initiated by setting RCR1.0 to 1 or externally transitioning RST
from low to high. Note that using RST to initiate a resync resets the output timing while RST is low; use
of RCR1.1 will not affect the output timing until the new alignment is located.
RESYNC (RCR1.0)
A 0-to-1 transition of RCR1.0 causes the synchronizer to search for the framing pattern sequence
immediately, regardless of the internal sync status. In order to initiate another resync command, this bit
must be cleared and then set again.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2186S | DATACOM, DIGITAL SLIC, PDSO20 |
| DS2187 | DATACOM, PCM TRANSCEIVER, PDIP18 |
| DS2196LN | DATACOM, FRAMER, PQFP100 |
| DS21FF44 | DATACOM, FRAMER, PBGA300 |
| DS21FF44N | DATACOM, FRAMER, PBGA300 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2182AQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM， Other/Special/Miscellaneous |
| DS2182N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2182Q | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2182Q/T&R | 制造商:Maxim Integrated Products 功能描述:T1 LINE MONITOR-PLCC-TRL - Tape and Reel |
| DS2182Q/T&R | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。