參數(shù)資料
型號(hào)： DS2151QB
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQCC44
封裝： 0.652 INCH, PLASTIC, LCC-44
文件頁(yè)數(shù)： 56/62頁(yè)
文件大?。?/td> 921K
代理商： DS2151QB
DS2151Q
6 of 60
2 PIN DESCRIPTION
PIN
NAME
TYPE
FUNCTION
1–4,
41–44
AD4–AD7,
AD0–AD3
I/O
Address/Data Bus. An 8-bit multiplexed address/data bus.
5
RD(DS)
I
Active-Low Read Input (Data Strobe)
6
CS
I
Active-Low Chip Select. Must be low to read or write the port.
7
ALE(AS)
I
Address Latch Enable (Address Strobe). A positive going edge serves to
demultiplex the bus.
8
WR(R/W)
I
Active-Low Write Input (Read/Write)
9
RLINK
O
Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or
Z bits (ZBTSI) one RCLK before the start of a frame. See Section 14 for
timing details.
10
RLCLK
O
Receive Link Clock. 4kHz or 2kHz (ZBTSI) demand clock for the RLINK
output. See Section 14 for timing details.
11
DVSS
—
Digital Signal Ground. 0.0V. Should be tied to local ground plane.
12
RCLK
O
Receive Clock. Recovered 1.544MHz clock.
13
RCHCLK
O
Receive Channel Clock. 192kHz clock that pulses high during the LSB of
each channel. Useful for parallel to serial conversion of channel data,
locating Robbed-Bit signaling bits, and for blocking clocks in DDS
applications. See Section 14 for timing details.
14
RSER
O
Receive Serial Data. Received NRZ serial data, updated on rising edges of
RCLK or SYSCLK.
15
RSYNC
I/O
Receive Sync. An extracted pulse, one RCLK wide, is output at this pin,
which identifies either frame (RCR2.4 = 0) or multiframe boundaries
(RCR2.4 = 1). If set to output frame boundaries, then via RCR2.5, RSYNC
can also be set to output double-wide pulses on signaling frames. If the
elastic store is enabled via the CCR1.2, then this pin can be enabled to be
an input via RCR2.3 at which a frame boundary pulse is applied. See
Section 14 for timing details.
16
RLOS/LOT
C
O
Receive Loss of Sync/Loss of Transmit Clock. A dual function output. If
CCR3.5 = 0, will toggle high when the synchronizer is searching for the T1
frame and multiframe; if CCR3.5 = 1, will toggle high if the TCLK pin has
not toggled for 5
s.
17
SYSCLK
I
System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic
store functions are enabled via either CCR1.7 or CCR1.2. Should be tied
low in applications that do not use the elastic store. If tied high for more
than 100
s, will force all output pins (including the parallel port) to tri-
state.
18
RCHBLK
O
Receive Channel Block. A user-programmable output that can be forced
high or low during any of the 24 T1 channels. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all T1
channels are used such as Fractional T1, 384kbps service, 768kbps, or
ISDN-PRI. Also useful for locating individual channels in drop-and-insert
applications. See Section 14 for timing details.
19
ACLKI
I
Alternate Clock Input. Upon a receive carrier loss, the clock applied at
this pin (normally 1.544MHz) will be routed to the RCLK pin. If no clock
is routed to this pin, then it should be tied to DVSS via a 1k
resistor.
相關(guān)PDF資料
PDF描述
DS2152LN DATACOM, FRAMER, PQFP100
DS2152L DATACOM, FRAMER, PQFP100
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DS21554L DATACOM, PCM TRANSCEIVER, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2151QB/T&R 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel
DS2151QB/T&R+ 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel
DS2151QB/T&R 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2151QB+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2151QB+T&R 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel
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