參數(shù)資料
型號： DS2148DK
廠商： Maxim Integrated Products
文件頁數(shù)： 40/73頁
文件大?。?/td> 0K
描述： KIT DESIGN LIU DS2148 3/5V T1/E1
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS2148
已供物品： 板
DS2148/DS21Q48
45 of 73
Table 6-4. Function of ECRS Bits and RNEG Pin
E1 or T1
(CCR1.7)
ECRS2
(CCR6.2)
ECRS1
(CCR6.1)
ECRS0
(CCR6.0)
RHBE
(CCR2.3)
FUNCTION OF ECR
COUNTERS/RNEG1
0
X
CVs
0
1
X
BPVs (HDB3 codewords not counted)
0
1
0
X
CVs + EXZs
0
1
X
BPVs + EXZs
1
0
X
0
BPVs (B8ZS codewords not counted)
1
0
X
1
0
BPVs + 8 EXZs
1
0
X
0
1
BPVs
1
0
X
1
BPVs + 16 EXZs
X
1
X
PRBS Errors2
NOTES:
1) RNEG outputs error data only when in NRZ mode (CCR1.6 = 1).
2) PRBS errors will always be output at PBEO independent of ECR control bits and NRZ mode and will
not be present at RNEG.
6.4.1 Error Counter Update
A transition of the ECUE (CCR1.4) control bit from 0 to 1 will update the ECR registers with the current
values and reset the counters. ECUE must be set back to zero and another 0 to 1 transition must occur for
subsequent reads/resets of the ECR registers. Note that the DS2148 can report errors at RNEG when in
NRZ mode (CCR1.6 = 1) by outputting a pulse for each error occurrence. The counter saturates at 65,535
and will not rollover.
ECR1 (11H): UPPER ERROR COUNT REGISTER 1
ECR2 (12H): LOWER ERROR COUNT REGISTER 2
(MSB)
(LSB)
E15
E14
E13
E12
E11
E10
E9
E8
ECR1
E7
E6
E5
E4
E3
E2
E1
E0
ECR2
SYMBOL
POSITION
DESCRIPTION
E15
ECR1.7
MSB of the 16-bit error count.
E0
ECR2.0
LSB of the 16-bit error count.
6.5 Error Insertion
When IBPV (CCR3.1) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion. See Figure 1-3 for details on the insertion of the BPV into the datastream.
When IBE (CCR3.0) is transitioned from a zero to a one, the device will insert a logic error. IBE must be
cleared and set again for another logic error insertion. See Figure 1-3 for details on the insertion of the
logic error into the datastream.
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