參數(shù)資料
型號： DS2148DK
廠商： Maxim Integrated Products
文件頁數(shù)： 17/73頁
文件大?。?/td> 0K
描述： KIT DESIGN LIU DS2148 3/5V T1/E1
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS2148
已供物品： 板
DS2148/DS21Q48
24 of 73
3.2 Parallel Port Operation
When using the parallel interface on the DS2148 (BIS1 = 0) the user has the option for either multiplexed
bus operation (BIS1 = 0, BIS0 = 0) or nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1). The DS2148
can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied low, Intel
timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed
in parentheses. See the timing diagrams in Section 10 for more details.
3.3 Serial Port Operation
Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS2148. Port read/write timing is
unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.
See Section 10 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 3-1,
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 5 bits identify the register address. Bit 7 is reserved and must
be set to 0 for proper operation.
The last bit (MSB) of the address/command byte is the burst mode bit. When the burst bit is enabled
(B = 1) and a READ operation is performed, addresses 0 through 15h are read sequentially, starting at
address 0h. And when the burst bit is enabled and a WRITE operation is performed, addresses 0 through
16h are written sequentially, starting at address 0h. Burst operation is stopped once address 15h is read.
See Figure 3-5 and Figure 3-6 for more details.
All data transfers are initiated by driving the
CS input low. When input clock-edge select (ICES) is low,
input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the
falling edge of SCLK. When output clock-edge select (OCES) is low, data is output on the falling edge of
SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next
falling or rising edge. All data transfers are terminated if the
CS input transitions high. Port control logic
is disabled and SDO is tri-stated when
CS is high.
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相關代理商/技術參數(shù)
參數(shù)描述
DS2148G 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148G+ 功能描述:網(wǎng)絡控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GB 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GN 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GN+ 功能描述:網(wǎng)絡控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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