參數(shù)資料
型號: DS1996L-F5
廠商: DALLAS SEMICONDUCTOR
元件分類: Memory IC:Other
英文描述: SPECIALTY MEMORY CIRCUIT, MADB2
封裝: MICRO CAN
文件頁數(shù): 4/18頁
文件大?。?/td> 321K
代理商: DS1996L-F5
DS1996
12 of 18
1-WIRE SIGNALING
The DS1996 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. All these signals except presence pulse are initiated by the bus master. The DS1996 can
communicate at two different speeds, regular speed and Overdrive speed. If not explicitly set into the
overdrive mode, the DS1996 will communicate at regular speed. While in Overdrive Mode the fast timing
applies to all wave forms.
The initialization sequence required to begin any communication with the DS1996 is shown in Figure 10.
A reset pulse followed by a presence pulse indicates the DS1996 is ready to send or receive data given the
correct ROM command and memory function command. The bus master transmits (TX) a reset pulse
(tRSTL , minimum 480 s at regular speed, 48 s at Overdrive speed). The bus master then releases the
line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor.
After detecting the rising edge on the data contact, the DS1996 waits (tPDH, 15-60 s at regular speed, 2-6
s at Overdrive speed) and then transmits the presence pulse (tPDL, 60-240 s at regular speed, 8-24 s at
Overdrive speed).
A Reset Pulse of 480 s or longer will exit the Overdrive Mode returning the device to regular speed. If
the DS1996 is in Overdrive Mode and the Reset Pulse is no longer than 80 s the device will remain in
Overdrive Mode.
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