參數(shù)資料
型號: DS1995
廠商: Maxim Integrated Products, Inc.
英文描述: 16Kbit Memory iButton(4K位存儲器按鈕)
中文描述: 16K位存儲器iButton®
文件頁數(shù): 1/4頁
文件大小: 45K
代理商: DS1995
F
a
Preliminary Specification
140 MSPS
Graphics Digitizer
AD9884
04/18/98
REV. 0
Analog Devices, Inc., 1998
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
One Technology Way, P.O Box 9106, Norwood, MA 02062–9106, USA
Tel: 617/329–4700
Fax: 617–326–8703
The AD9884 is a complete 8-bit 140MSPS, monolithic graphics
digitizer optimized for digitizing RGB graphics signals from
personal computers and workstations. Its 140MSPS encode rate
capability and full-power analog bandwidth of 300MHz supports
display resolutions of up to 1280 x 1024 at 75Hz with sufficient
input bandwidth to accurately acquire and digitize each pixel.
To minimize system cost and power dissipation, the AD9884
includes an internal +1.25V reference, PLL to generate a pixel
clock from HSYNC and VSYNC, and programmable gain and
clamp control. The user provides only a +3.3V power supply,
analog input, and HSYNC and VSYNC signals. Three-state
CMOS outputs may be powered from 2.5V to 3.3V.
The AD9884’s on-chip PLL generates a pixel clock from HSYNC
and VSYNC inputs. Pixel clock output frequencies range from 20–
140 MHz. PLL clock jitter is 500ps p-p typical relative to the input
reference. When an external COAST signal is presented, the PLL
maintains its output frequency in the absence of HSYNC. A
sampling phase adjustment is provided. Data, HSYNC and Clock
output phase relationships are maintained. The PLL can be
disabled and an external clock input provided as the pixel clock.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This device is fully
programmable via a two wire serial bus.
Fabricated in an advanced CMOS process, the AD9884 is
provided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over the 0°C to +85°C temperature range.
FEATURES
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5V to 1.0V Analog Input Range
500pS p-p PLL clock jitter
3.3V power supply
2.5V to 3.3V three-state CMOS outputs
Demultiplexed Output Ports
Data Clock Output Provided
Low Power : 800mW Typical
Internal PLL generates CLOCK from HSYNC
Serial bus interface
Fully programmable
Supports 2 pixels per clock mode
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Clamp
A/D
R
IN
R
OUTA
R
OUTB
8
8
8
Clamp
A/D
G
IN
G
OUTA
G
OUTB
8
8
8
Clamp
A/D
B
IN
B
OUTA
B
OUTB
8
8
8
Clock
Generator
HSYNC
VSYNC
CLAMP
CKINV
CKEXT
DATACK
PXCK
EVEN
HSOUT
2
2
Control
Ref
S
S
A
0
P
A
1
R
R
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