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REV 2.1 - Information Subject to Change
Analog Devices Inc., Proprietary & Confidential
6/5/98
Page 1 of 74
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Single-Chip, DSP-Based
High Performance Motor Controller
P
RELIMINARY
T
ECHNICAL
I
NFORMATION
ADMC401
F
EATURES
26 MIPS Fixed Point DSP Core
Single Cycle Instruction Execution (38.5 ns).
External 14-bit Address and 24-bit Data Bus.
ADSP-21xx Family Code Compatible.
16-bit Arithmetic & Logic Unit (ALU).
Hardware Multiply & Accumulate Unit (MAC).
Single Cycle 16-bit x 16-bit Multiply &
Accumulate into 40-bit Accumulator.
32-bit Shifter (Logical & Arithmetic).
Multifunction Instructions.
Single Cycle Context Switch.
Powerful Program Sequencer:
Zero Overhead Looping.
Conditional Instruction Execution.
Two Independent Data Address Generators.
Memory Configuration
2k x 24-bit Internal Program Memory RAM.
2k x 24-bit Internal Program Memory ROM.
1k x 16-bit Internal Data Memory RAM.
Address & Data Buses permit External Memory
Expansion.
High-Resolution Multichannel ADC System
12-bit Analog to Digital Converter.
Pipeline Flash Architecture.
8 Dedicated Analog Inputs.
All 8 Channels Converted in <2
μ
s.
Channels Sampled at 120 ns Intervals.
8 Dedicated, Memory-Mapped, 16-bit, 2’s
Complement Data Registers.
4.0 V peak-peak Input Voltage Range.
Ability to Synchronize Conversions to PWM.
Internal or External Convert Start.
Differential Non Linearity < 1 LSB.
Integral Non Linearity < 2 LSB.
Dedicated ADC Interrupt on end of Conversion.
Operation from Internal or External Reference.
Voltage Reference
Internal 2.5 V
±
1.0 % Voltage Reference.
Dedicated VREF pin.
Three-Phase PWM Generation Subsystem
16-bit Dedicated PWM Generator.
Edge Resolution to 38.5 ns.
Programmable Dead Time.
Programmable Minimum Pulse Width.
Double Update Mode Allows Duty Cycle & Period
Adjustment on Half Cycle Boundaries.
Special Features for Brushless DC & Switched
Reluctance Motors.
Hardware Polarity Control.
External Dedicated Asynchronous Shutdown Pin
(
PWMTRIP
).
Additional Shutdown Pins in I/O System.
Individual Enable/Disable of Each Output.
High-Frequency Chopping Mode.
Transparent Transition to Over-Modulation Range
with Duty Cycles of 100%.
Capability to Drive Optocouplers Directly (10 mA
Sink & Source Capability).
Flexible Encoder Interface Subsystem
Incremental Encoder Interface.
Dedicated Interface (Quadrature and Index Signals).
Alternative Frequency and Direction Inputs.
Programmable Filtering of Encoder Input Signals.
Glitch Detection.
16-bit Quadrature Counter.
Input Encoder Signals to 3.25 MHz.
Programmable MAXCNT Register.
Two Inputs Permit Latching of Encoder Counter
Value on External Triggers.
Optional Hardware Reset of Counter.