參數(shù)資料
型號(hào)： DS1986-F5
廠商： DALLAS SEMICONDUCTOR
元件分類(lèi)： Programmable ROM
英文描述： 64K X 1 OTPROM, MADB2
封裝： MICROCAN-2
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 548K
代理商： DS1986-F5
DS1986
15 of 27
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an
open drain connection or 3-state outputs. The DS1986 is an open drain part with an internal circuit
equivalent to that shown in Figure 6. The bus master can be the same equivalent circuit. If a bidirectional
pin is not available, separate output and input pins can be tied together.
The bus master requires a pull-up resistor at the master end of the bus, with the bus master circuit
equivalent to the one shown in Figures 7a and 7b. The value of the pull-up resistor should be
approximately 5k
for short line lengths.
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At regular speed the 1-Wire bus
has a maximum data rate of 16.3k bits per second. The speed can be boosted to 142k bits per second by
activating the Overdrive mode. If the bus master is also required to perform programming of the EPROM
portions of the DS1986, a programming supply capable of delivering up to 10 milliamps at 12 volts for
480
s is required. The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be
suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and
the bus is left low for more than 16
s (overdrive speed) or more than 120 s (regular speed), one or more
of the devices on the bus may be reset.
Transaction Sequence
The sequence for accessing the DS1986 via the 1-Wire port is as follows:
§ Initialization
§ ROM Function Command
§ Memory Function Command
§ Read/Write Memory/Status
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the
slave(s).
The presence pulse lets the bus master know that the DS1986 is on the bus and is ready to operate. For
more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the six ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in
Figure 8):
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS1986-F5# 功能描述:iButton RoHS:否 存儲(chǔ)類(lèi)型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類(lèi)型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated
DS1986-F5+ 功能描述:iButton RoHS:否 存儲(chǔ)類(lèi)型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類(lèi)型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated
DS1986U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UniqueWare iButton
DS1990 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Serial Number iButton
DS1990A 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Serial Number iButton
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