參數(shù)資料
型號: DS1842N+T&R
廠商: Maxim Integrated
文件頁數(shù): 4/7頁
文件大?。?/td> 210K
描述: IC CURRENT MONITOR 14TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 電流監(jiān)控器
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 14-TDFN-EP(3x3)
包裝: 帶卷 (TR)
76V, APD, Bias Output Stage with
Current Monitoring
4  _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(T
A
= +25癈, unless otherwise noted.)
FET ON-RESISTANCE vs. DRAIN CURRENT
I
DS
 (mA)
100
10
4
5
6
7
3
1
1000
V
GS
 = 2.5V
V
GS
 = 3.0V
V
GS
 = 3.6V
V
GS
 = 5V
V
GS
 = 10V
FET DRAIN CURRENT vs. DRAIN VOLTAGE
DRAIN VOLTAGE (V)
3
2
1
100
200
300
400
500
600
700
0
0
4
V
GS
 = 2.5V
V
GS
 = 3.0V
V
GS
 = 3.6V
V
GS
 = 5V
V
GS
 = 10V
Pin Description
PIN
NAME
FUNCTION
1
MIR1     Current Mirror Monitor Output, 10:1 Ratio
2
MIR2     Current Mirror Monitor Output, 5:1 Ratio
3
N.C.
No Connection. Can be connected to
GND for compatibility with the DS1842A.
4,
912
N.C.
No Connection. Not internally
connected.
5
CLAMP
Clamp Input. Disables the current mirror
output (MIROUT).
6
GATE
FET Gate Connection
7
GND
Ground
8
LX
FET Drain Connection. Connect to
switching inductor.
13
MIRIN    Current Mirror Input
14
MIROUT
Current Mirror Output. Connect to APD
bias pin.

EP
Exposed Pad. Connect to ground.
Block Diagram
DS1842
LX
GATE
GND
MIRIN
MIR1
CLAMP
MIROUT
CURRENT MIRROR
CURRENT
LIMIT
MIR2
THERMAL
SHUTDOWN
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