參數(shù)資料
型號(hào): DS17887-5
英文描述: Real-Time Clock
中文描述: 實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù): 19/38頁(yè)
文件大?。?/td> 515K
代理商: DS17887-5
DS17885/DS17887
19 of 38
RAM CLEAR
The DS17885/DS17887 provides a RAM clear function for the 114 bytes of user RAM. When enabled,
this function can be performed regardless of the condition of the V
CC
pin.
The RAM clear function is enabled or disabled via the RAM Clear Enable bit (RCE; bank 1, register
04BH). When this bit is set to a logic 1, the 114 bytes of user RAM will be cleared (all bits set to 1)
when an active low transition is sensed on the
RCLR
pin. This action will have no effect on either the
clock/calendar settings or upon the contents of the extended RAM. The RAM clear Flag (RF, bank 1,
register 04AH) will be set when the RAM clear operation has been completed. If V
CC
is present at the
time of the RAM clear and RIE=1, the
IRQ
line will also be driven low upon completion. The interrupt
condition can be cleared by writing a zero to the RF bit. The
IRQ
line will then return to its inactive high
level provided there are no other pending interrupts. Once the
RCLR
pin is activated, all read/write
accesses are locked out for a minimum recover time, specified as t
REC
in the Electrical Characteristics
section.
When RCE is cleared to 0, the RAM clear function is disabled. The state of the
RCLR
pin will have no
effect on the contents of the user RAM, and transitions on the
RCLR
pin have no effect on RF.
8k X 8 EXTENDED RAM
The DS17885/DS17887 provides 8k x 8 of on-chip SRAM which is controlled as nonvolatile storage
sustained from a lithium battery. On power-up, the RAM is taken out of write protect status by the
internal power OK signal (POK) generated from the write protect circuitry.
The on-chip 8k x 8 nonvolatile SRAM is accessed via the eight multiplexed address/data lines AD7 to
AD0. Access to the SRAM is controlled by three on-chip latch registers. Two registers are used to hold
the SRAM address, and the other register is used to hold read/write data. The SRAM address space is
from 00h to 01FFFh.
Access to the extended 8k x 8 RAM is controlled via three of the Dallas registers shown in Figure 4. The
Dallas registers in bank 1 must first be selected by setting the DV0 bit in register A to a logic 1. The
13-bit address of the RAM location to be accessed must be loaded into the extended RAM address
registers located at 50h and 51h. The least significant address byte should be written to location 50h, and
the most significant 5-bits (right-justified) should be loaded in location 51h. Data in the addressed
location may be read by performing a read operation from location 53h, or written to by performing a
write operation to location 53h. Data in any addressed location may be read or written repeatedly without
changing the address in location 50h and 51h.
To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment
the extended RAM address. To enable the burst mode feature, set the BME bit in the extended control
register 4Ah, to a logic 1. With burst mode enabled, write the extended RAM starting address location to
registers 50h and 51h. Then read or write the extended RAM data from/to register 53h. The extended
RAM address locations are automatically incremented on the rising edge of
RD
or
WR
only when
register 53h is being accessed. Refer to the Burst Mode Timing Waveform.
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