參數(shù)資料
型號(hào): DS1775R7+T&R
廠商: Maxim Integrated
文件頁(yè)數(shù): 4/14頁(yè)
文件大?。?/td> 394K
描述: IC THERMOM/STAT DIG 111 SOT-23-5
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 3,000
功能: 溫度計(jì),恒溫計(jì)
傳感器類型: 內(nèi)部
感應(yīng)溫度: -55°C ~ 125°C
精確度: ±3°C(最小值)
拓?fù)洌?/td> ADC,比較器,寄存器庫(kù)
輸出類型: I²C?/SMBus?
輸出警報(bào):
輸出風(fēng)扇: 無(wú)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應(yīng)商設(shè)備封裝: SOT-23-5
包裝: 帶卷 (TR)
DS1775
 
 
4 of 14
 
Table 2. Temperature/Data Relationships
 
S
2
6
 
2
5
 
2
4
 
2
3
 
2
2
 
2
1
 
2
0
 
MSB
MSb
 
 
UNIT = 癈
 
 
LSb
 
2
-1
 
2
-2
 
2
-3
 
2
-4
 
0
0
0
0
LSB
 
TEMPERATURE
?SPAN class="pst DS1775R7-T-R_2292811_1">C  
DIGITAL OUTPUT
BINARY
DIGITAL OUTPUT
HEX
+125
0111 1101 0000 0000
7D00h
+25.0625
0000 1010 0010 0000
1910h
+10.125
0000 1010 0010 0000
0A20h
+0.5
0000 0000 1000 0000
0080h
0
0000 0000 0000 0000
0000h
-0.5
1111 1111 1000 0000
FF80h
-10.125
1111 0101 1110 0000
F5E0h
-25.0625
1110 0110 1111 0000
E6F0h
-55
1100 1001 0000 0000
C900h
 
Thermostat Control
In its comparator operating mode, the DS1775 functions as a thermostat with programmable hysteresis, as
shown in Figure 2. When the DS1775s temperature meets or exceeds the value stored in the high
temperature trip register (T
OS
) a consecutive number of times, as defined by the configuration register, the
output becomes active and stays active until the first time that the temperature falls below the temperature
stored in the low temperature trigger register (T
HYST
). In this way, any amount of hysteresis may be
obtained. The DS1775 powers up in the comparator mode with T
OS
 = +80癈 and T
HYST
 = +75癈 and can
be used as a stand-alone thermostat (no 2-wire interface required) with those setpoints.
 
In the interrupt mode, the O.S. output first becomes active following the programmed number of
consecutive conversions above T
OS
. The fault can only be cleared by either setting the DS1775 in a
shutdown mode or by reading any register (temperature, configuration, T
OS
, or T
HYST
) on the device.
Following a clear, a subsequent fault can only occur if consecutive conversions fall below T
HYST
. This
interrupt/clear process is thus cyclical (T
OS
, clear, T
HYST
, clear, T
OS
, clear, T
HYST
, clear, etc.). Only the
first of multiple consecutive T
OS
 violations activates O.S., even if each fault is separated by a clearing
function. The same situation applies to multiple consecutive T
HYST
 events.
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