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參數(shù)資料
| 型號(hào)： | DS1775R7+T&R |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 394K |
| 描述： | IC THERMOM/STAT DIG 111 SOT-23-5 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | 溫度計(jì)，恒溫計(jì) |
| 傳感器類型： | 內(nèi)部 |
| 感應(yīng)溫度： | -55°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓?fù)洌?/td> | ADC，比較器，寄存器庫 |
| 輸出類型： | I²C?/SMBus? |
| 輸出警報(bào)： | 是 |
| 輸出風(fēng)扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 帶卷 (TR) |
DS1775
12 of 14
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(V
DD
= 2.7V to 5.5V, T
A
= -55癈 to +125癈, unless otherwise noted.) (Figure 5)
PARAMETER
SYMBOL CONDITIONS
MIN TYP MAX UNITS NOTES
SCL Clock Frequency
f
SCL
Fast mode
400
kHz
Standard mode
100
Bus Free Time
Between a STOP and
START Condition
t
BUF
Fast mode
1.3
祍
Standard mode
4.7
Hold Time (Repeated)
START Condition
t
HD:STA
Fast mode
0.6
祍
5
Standard mode
4.0
Low Period of SCL
t
LOW
Fast mode
1.3
祍
Standard mode
4.7
High Period of SCL
t
HIGH
Fast mode
0.6
祍
Standard mode
4.0
Setup Time for a
Re eated START
t
SU:STA
Fast mode
0.6
祍
Standard mode
4.7
Data Hold Time
t
HD:DAT
Fast mode
0
0.9
祍
6
Standard mode
0
0.9
Data Setup Time
t
SU:DAT
Fast mode
100
ns
7
Standard mode
250
Rise Time of Both SDA
and SCL Si nals
t
R
Fast mode
20 + 0.1C
B
300
ns
8
Standard mode
20 + 0.1C
1000
Fall Time of Both SDA
and SCL Si nals
t
F
Fast mode
20 + 0.1C
B
300
ns
8
Standard mode
20 + 0.1C
300
Setup Time for STOP
t
SU:STO
Fast mode
0.6
祍
Standard mode
4.0
Capacitive Load for
Each Bus Line
C
B
400
pF
8
In ut Ca acitance
C
5
F
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
DD
is switched off.
3. I
DD
specified with O.S. pin open.
4. I
DD
specified with V
DD
at 5.0V and V
SDA
, V
SCL
= 5.0V, 0癈 to +70癈.
5. After this period, the first clock pulse is generated.
6. The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the
SCL signal.
7. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
e 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL
signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit
to the SDA line t
R MAX
+t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
8. C
B
= Total capacitance of one bus line in pF.
9. Internal heating caused by O.S. loading causes the DS1775 to read approximately 0.5篊 higher if O.S.
is sinking the max rated current.
10. Contact the factory for operation requiring temperature readings greater than +120癈.
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