參數(shù)資料
型號: DS1742-70
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP24
封裝: 0.740 INCH, ENCAPSULATED, DIP-24
文件頁數(shù): 9/15頁
文件大小: 727K
代理商: DS1742-70
DS1742
3 of 15
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All of the DS1742 registers are updated simultaneously after the internal clock
register updating process has been re-enabled. Updating is within a second after the read bit is written to
0. The READ bit must be a zero for a minimum of 500
μs to ensure the external registers will be updated.
Figure 1. DS1742 BLOCK DIAGRAM
Table 1. TRUTH TABLE
VCC
CE
OE
WE
MODE
DQ
POWER
VIH
X
Deselect
High-Z
Standby
VIL
X
VIL
Write
Data In
Active
VIL
VIH
Read
Data Out
Active
VCC > VPF
VIL
VIH
Read
High-Z
Active
VSO < VCC < VPF
X
Deselect
High-Z
CMOS Standby
VCC < VSO < VPF
X
Deselect
High-Z
Data Retention Mode
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相關代理商/技術參數(shù)
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