參數(shù)資料
型號(hào): DS1742-70
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP24
封裝: 0.740 INCH, ENCAPSULATED, DIP-24
文件頁數(shù): 11/15頁
文件大?。?/td> 727K
代理商: DS1742-70
DS1742
5 of 15
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable
access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE , and OE . If the
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE on CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The
3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When
VCC falls below the power fail point, VPF, access to the device is inhibited. If VPF is less than Vso, the
device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is
greater than Vso, the device power is switched from VCC to the backup supply (VBAT) when VCC drops
below Vso. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
相關(guān)PDF資料
PDF描述
DS1742W-150 0 TIMER(S), REAL TIME CLOCK, DMA24
DS1743P-70 0 TIMER(S), REAL TIME CLOCK, DMA34
DS1743-70 0 TIMER(S), REAL TIME CLOCK, DMA28
DS1743W-120 0 TIMER(S), REAL TIME CLOCK, DMA28
DS9034PCX 0 TIMER(S), REAL TIME CLOCK, DMA34
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS1742-85 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Y2KC Nonvolatile Timekeeping RAMwww.
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DS1742W-120+ 功能描述:實(shí)時(shí)時(shí)鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube