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參數(shù)資料
| 型號： | DS17285EN-3 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | TSOP-28 |
| 文件頁數(shù)： | 10/38頁 |
| 文件大小： | 415K |
| 代理商： | DS17285EN-3 |
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DS17285/DS17287
18 of 38
Also at this time, the Kickstart Flag (KF, bank 1, register 04AH) will be set, indicating that a kickstart
condition has occurred.
The timing associated with both the wake-up and kickstarting sequences is illustrated in the Wake-Up /
Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing
associated with these functions is divided into 5 intervals, labeled 1-5 on the diagram.
The occurrence of either a kickstart or wake-up condition will cause the PWR pin to be driven low, as
described above. During interval 1, if the supply voltage on the DS17285/DS17287 VCC pin rises above
the greater of VBAT or VPF before the power on timeout period (tPOTO) expires, then PWR will remain at
the active low level. If VCC does not rise above the greater of VBAT or VPF in this time, then the PWR
output pin will be turned off and will return to its high impedance level. In this event, the IRQ pin will
also remain tri-stated. The interrupt flag bit (either WF or KF) associated with the attempted power on
sequence will remain set until cleared by software during a subsequent system power on.
If VCC is applied within the timeout period, then the system power on sequence will continue as shown in
intervals 2-5 in the timing diagram. During interval 2, PWR will remain active and IRQ will be driven to
its active low level, indicating that either WF or KF was set in initiating the power on. In the diagram KS
is assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit will be automatically
cleared to 0 in response to a successful power on. The PWR line will remain active as long as the PAB
remains cleared to 0.
At the beginning of interval 3, the system processor has begun code execution and clears the interrupt
condition of WF and/or KF by writing zeroes to both of these control bits. As long as no other interrupt
within the DS17285/DS17287 is pending, the IRQ line will be taken inactive once these bits are reset.
Execution of the application software may proceed. During this time, both the wake-up and kickstart
functions may be used to generate status and interrupts. WF will be set in response to a date, hours,
minutes, and seconds match condition. KF will be set in response to a low going transition on KS . If the
associated interrupt enable bit is set (WIE and/or KSE) then the IRQ line will driven active low in
response to enabled event. In addition, the other possible interrupt sources within the DS17285/DS17287
may cause IRQ to be driven low. While system power is applied, the on chip logic will always attempt to
drive the PWR pin active in response to the enabled kickstart or wake-up condition. This is true even if
PWR
was previously inactive as the result of power being applied by some means other than wake-up or
kickstart.
The system may be powered down under software control by setting the PAB bit to a logic 1. This causes
the open-drain PWR pin to be placed in a high impedance state, as shown at the beginning of interval 4 in
the timing diagram. As VCC voltage decays, the IRQ output pin will be placed in a high impedance state
when VCC goes below VPF. If the system is to be again powered on in response to a wake-up or kickstart,
then the both the WF and KF flags should be cleared and WIE and/or KSE should be enabled prior to
setting the PAB bit.
During interval 5, the system is fully powered down. Battery backup of the clock calendar and
nonvolatile RAM is in effect and IRQ is tri-stated, and monitoring of wake-up and kickstart takes place.
If PRS=1, PWR stays active, otherwise if PRS=0 PWR is tri-stated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS17285S-3 | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| DS1742-100 | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| DS1742W-120 | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| DS1742-70 | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| DS1742W-150 | 0 TIMER(S), REAL TIME CLOCK, DMA24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS17285EN-3+ | 功能描述:實(shí)時(shí)時(shí)鐘 3V/5V RTC K Multiplexed Kick-S RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS17285EN-5 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3V/5V Real-Time Clock |
| DS17285N-3 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3V/5V Real-Time Clock |
| DS17285N5 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Real-Time Clocks |
| DS17285N-5 | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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