參數(shù)資料
型號: DS1689SN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 31/36頁
文件大?。?/td> 0K
描述: IC RTC SER NV RAM CTRL IN 28SOIC
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/日歷
特點(diǎn): NVSRAM
存儲容量: 114B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 2.7 V ~ 3.3 V,4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 帶卷 (TR)
DS1689/DS1693
4 of 36
PIN
SO
EDIP
NAME
FUNCTION
24
SQW
Square-Wave Output. The SQW pin can output a signal from one of
13 taps provided by the 15 internal divider stages of the real time
clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 2. The SQW signal can
be turned on and off using the SQWE bit in Register B. A 32kHz
SQW signal is output when SQWE = 1, the Enable 32kHz (E32K)
bit in extended register 04BH is logic 1, and VCC is above VPF. A
32kHz square wave is also available when VCC is less than VPF if
E32K = 1, ABE = 1, and voltage is applied to VBAUX.
25
VCCO
External SRAM Power-Supply Output. This pin is internally
connected to VCCI when VCCI is within nominal limits. However,
during power fail, VCCO is internally connected to the VBAT or VBAUX
(whichever is larger). For 5V operation, switchover from VCCI to the
backup supply occurs when VCCI drops below the larger of VBAT and
VBAUX. For 3V operation, switchover from VCCI to the backup supply
occurs at VPF if VPF is less than VBAT and VBAUX. If VPF is greater
than VBAT and VBAUX, the switch from VCCI to the backup supply
occurs when VCCI drops below the larger of VBAT and VBAUX.
26
VCCI
+3V or +5V Main Supply. DC power is provided to the device on
these pins. 5V operation is selected when the PSEL pin is at logic 1.
If PSEL is floated or at logic 0, the device is in autosense mode and
determines the correct operating voltage based on the VCCI voltage
level.
27
CEO
Active-Low RAM Chip Enable Output. When power is valid,
CEO
will equal
CEI. When power is not valid, CEO will be driven high
regardless of
CEI.
28
CEI
Active-Low RAM Chip Enable Input.
CEI should be driven low to
enable the external RAM.
2, 3,
19, 23
N.C.
No Connection
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