參數(shù)資料
型號: DS1682S
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), TIME RECORDER, PDSO8
封裝: 0.150 INCH, SOP-8
文件頁數(shù): 6/14頁
文件大?。?/td> 202K
代理商: DS1682S
DS1682 Total-Elapsed-Time Recorder with Alarm
14 of 14
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
M a x i m In tegra t ed P r oduc ts , 1 2 0 S a n Ga brie l D r iv e , Sun n y vale , CA 94 086 40 8 - 7 3 7 - 76 00
2005 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
TIMING DIAGRAM
Note 1:
Typical values are at +25°C, VCC = 4.0V.
Note 2:
The elapsed time and event counters are backed by three EEPROM arrays, which are used
sequentially, allowing up to 3 x EE. The configuration register, alarm trip-point register and user
memory use a single array, limiting them to one EE.
Note 3:
A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended.
A typical value is 0.01μF. VCC must be maintained above VCC minimum, including transients, during
EEPROM writes.
Note 4:
VCC must be at or above 2.5V for tEW after the end of an event to ensure data transfer to the EEPROM.
Note 5:
Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.
Note 6:
After this period, the first clock pulse is generated.
Note 7:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 8:
The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL
signal.
Note 9:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must
be met. This is automatically the case if the device does not stretch the tLOW. If such a device does
stretch tLOW, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 10:
CB—total capacitance of one bus line in pF.
CHIP INFORMATION
TRANSISTOR COUNT: 26,032
PROCESS: CMOS
PACKAGE INFORMATION
For the latest package information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 SO
S8+5
相關(guān)PDF資料
PDF描述
DS1682 0 TIMER(S), TIME RECORDER, PDSO8
DS1685-3 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS1687-5 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS1685Q-3 1 TIMER(S), REAL TIME CLOCK, PQCC28
DS1685S-3 1 TIMER(S), REAL TIME CLOCK, PDSO24
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