參數(shù)資料
型號(hào): DS1682S+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/14頁(yè)
文件大?。?/td> 0K
描述: IC TIMEKEEPER ALARM ELAPSE 8SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 耗用時(shí)間計(jì)數(shù)器
特點(diǎn): 警報(bào)器,EEPROM
存儲(chǔ)容量: 10B
時(shí)間格式: 二進(jìn)制
數(shù)據(jù)格式: 二進(jìn)制
接口: I²C,2 線串口
電源電壓: 2.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
Depending upon the state of the R/W bit, two types of
data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received
byte.
Data transfer from a slave transmitter to a master
receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit. Next
follows a number of data bytes transmitted by the slave to
the master. The master returns an acknowledge bit after
all received bytes other than the last byte. A “not acknowl-
edge” is returned at the end of the last received byte.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condi-
tion. Since a repeated START condition is also the begin-
ning of the next serial transfer, the bus is not released.
Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte
is received, the receiver transmits an acknowledge bit.
START and STOP conditions are recognized as the begin-
ning and end of a serial transfer. The slave address byte is
the first byte received after the master generates a START
condition. The address byte contains the 7-bit DS1682
address, which is 1101011 (D6h), followed by the direction
bit (R/W). The second byte from the master is the register
address. This sets the register pointer. The master then
transmits each byte of data, with the DS1682 acknowledg-
ing each byte received. The register pointer increments
after each byte is written. The master generates a STOP
condition to terminate the data write (Figure 7).
Slave Transmitter Mode (Read Mode): The first byte
is received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the DS1682 while the serial clock is input on SCL.
The slave address byte is the first byte received after the
master generates a START condition. The address byte
contains the 7-bit DS1682 address, followed by the direc-
tion bit (R/W). After receiving a valid slave address byte
and direction bit, the DS1682 generates an acknowledge
on the SDA line. The DS1682 begins to transmit data on
each SCL pulse starting with the register address pointed
to by the register pointer. As the master reads each byte,
it must generate an acknowledge. The register pointer
increments after each byte is read. The DS1682 must
receive a “not acknowledge” on the last byte to end a
read (Figure 8).
Figure 7. Data Write—Slave Receiver Mode
Figure 8. Data Read—Slave Transmitter Mode
R/W
R/W – READ/WRITE OR DIRECTION BIT
S
1101011
0
A
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
P
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
SLAVE
ADDRESS
REGISTER
ADDRESS
S – START
A – ACKNOWLEDGE
P – STOP
DATA (n)
DATA (n + 1)
DATA (n + x)
R/W
/A – NOT ACKNOWLEDGE
S
1101011
1
A
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
/A
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
SLAVE
ADDRESS
S – START
A – ACKNOWLEDGE
P – STOP
DATA (n + 1)
DATA (n)
DATA (n + 2)
DATA (n + x)
R/W – READ/WRITE OR DIRECTION BIT
DS1682
Total-Elapsed-Time Recorder
with Alarm
www.maximintegrated.com
Maxim Integrated │ 12
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