參數(shù)資料
型號: DS1678
廠商: DALLAS SEMICONDUCTOR
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP8
封裝: 0.300 INCH, DIP-8
文件頁數(shù): 8/24頁
文件大?。?/td> 301K
代理商: DS1678
DS1678
16 of 24
2-WIRE SERIAL DATA BUS
The DS1678 supports a bi-directional two-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that
controls the message is called a "master". The devices that are controlled by the master are "slaves". The
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1678 operates as a slave on the two-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (See Figure 3):
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit. Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz
clock rate) are defined. The DS1678 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
相關(guān)PDF資料
PDF描述
DS1682S 0 TIMER(S), TIME RECORDER, PDSO8
DS1682 0 TIMER(S), TIME RECORDER, PDSO8
DS1685-3 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS1687-5 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS1685Q-3 1 TIMER(S), REAL TIME CLOCK, PQCC28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS1678J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-Input Digital Multiplexer
DS1678J/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-Input Digital Multiplexer
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