
DS1678
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ADDRESS POINTER REGISTER
The Address Pointer register always contains the address that the next data LSB will be written to in the
Event Log memory. The Address Pointer registers are located in the main memory map at LSB (3Fh)
and MSB (40h). These will be helpful in recovering all of the data if a rollover occurs. The address
pointer will point to the oldest event in the memory after a rollover. This is the memory location that
would be over written by the next event. Read the data from this point to the end of the memory and the
Start Time Stamp including the two Byte ETC from Last Event in order to recover all of the data in the
correct order.
GLITCH CONTROL CIRCUIT
The DS1678 has a built in glitch control circuit to filter noise on the INT pin from triggering false events.
A minimum of one internal clock cycle (0.122 ms) up to a maximum of two internal clock cycles
(0.245 ms) are required to recognize a transition on the input as an event. An event then requires an
additional seven to eight internal clock cycles (0.854 ms to 0.977 ms) to be processed and recorded into
memory. This means that the minimum event occurrence that can be recognized by the DS1678 requires
eight to ten internal clock cycles (0.976 ms to 1.22 ms). Failure to ensure this timing will cause the event
to be ignored. Thus, it is recommended that you design with the maximum timing specs.
The INT pin has a weak internal pull-down resistor to prevent the pin from floating if the signal
connected to the pin is tri-stated. Without the resistor, the input would float and potentially log phantom
events. With the pull-down resistor, the pin can be transitioned to a low state causing an event to be
recorded if the INT pin was being held high by an outside signal that becomes tri-stated.
SECURITY
The DS1678 provides several measures to insure data integrity for the end user. These security measures
are intended to prevent third party intermediaries from tampering with the data that has been stored in the
Event Log memory.
As a first security measure, the Event Log memory is Read-only from the perspective of the end user.
The DS1678 can write the data into these memory banks, but the end user cannot write data to individual
registers. This prevents an unscrupulous intermediary from writing false data to the DS1678. The end
user, however, can clear the contents of the Event Log Memory. A new mission can not be started unless
the MEM CLR bit has been set to a 1 to indicate that the memory and registers are cleared.
As a second security measure, changing any value in the memory including the RTC and Control
registers will stop event logging and clear the Mission-in-Progress (MIP) and Mission Enable (ME) bits.
The MEM CLR bit must be set to 1 so that the memory and registers are cleared before a new event log
mission can begin.
POWER CYCLING
When VCC falls below 1.25 x VBAT the device automatically write protects itself, terminates any access in
progress and resets the device address counter. Inputs to the device via the 2-wire bus will not be
recognized at this time to prevent erroneous data from being written to the device from an out of tolerance
system. When VCC falls below VBAT the device switches into a low-current battery backup mode. Upon
power up, the device switches from battery power to VCC when VCC is greater than VBAT+0.2V and
recognizes inputs from the system when VCC is greater than 1.25 x VBAT by releasing control of the write
protection on the 2-wire bus.