- 您現(xiàn)在的位置：買賣IC網 > PDF目錄9359 > DS1673S-5+T&R (Maxim Integrated Products)IC CTRLR SYSTEM PORT 5V 20-SOIC PDF資料下載
參數資料
| 型號： | DS1673S-5+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 16/18頁 |
| 文件大小： | 0K |
| 描述： | IC CTRLR SYSTEM PORT 5V 20-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 類型： | 便攜系統(tǒng)控制器 |
| 特點： | 警報器，閏年，監(jiān)視計時器 |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數據格式： | YY-MM-DD-dd |
| 接口： | 3 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1673
7 of 18
STATUS REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CU
LOBAT
0
IRQF
CU (Conversion Update In Progress). When this bit is a 1, an update to the ADC Register (register
0Eh) will occur within 488
s. When this bit is a 0, an update to the ADC Register will not occur for at
least 244
s.
LOBAT (Low Battery Flag). This bit reflects the status of the backup power source connected to the
VBAT pin. When VBAT is greater than 2.5V, LOBAT is set to a logic 0. When VBAT is less than 2.3V,
LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag). A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP DEFAULT STATES
These bits are set to a one upon initial power-up: EOSC , TD1 and TD0. These bits are cleared upon
initial power-up: WP, AIS1, and AIS0.
NONVOLATILE SRAM CONTROLLER
The DS1673 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the VCCO
pin. The DS1673 was specifically designed with the Intel 80186 and 386EX microprocessors in mind. As
such, the DS1673 has the capability to provide access to the external SRAM in either byte-wide or word-
wide format. This capability is provided by the chip enable scheme. Three input signals and two output
signals are used for enabling the external SRAM(s) (see Figure 4). CEI (chip enable in), BHE (byte high
enable), and BLE (byte low enable) are used for enabling either one or two external SRAMs through the
CEOL
(chip enable low) and the CEOH (chip enable high) outputs. Table 3 illustrates the function of
these pins.
The DS1673 nonvolatilizes the external SRAM(s) by write-protecting the SRAM(s) and by providing a
back-up power supply in the absence of VCC. When VCC falls below VPF, access to the external SRAM(s)
are prohibited by forcing CEOL and CEOH high regardless of the level of CEI , BLE , and BHE . Upon
power-up, access is prohibited until the end of tRPU.
EXTERNAL SRAM CHIP ENABLE Table 3
CEI
BHE
BLE
CEOL
CEOH
FUNCTION
0
Word transfer
0
1
0
Byte transfer in upper half of data bus (D15-D8)
0
1
0
1
Byte transfer in lower half of data bus (D7-D0)
0
1
External SRAMs disabled
1
X
1
External SRAMs disabled
相關PDF資料 |
PDF描述 |
|---|---|
| DS1806E-010+ | IC POT DIG SEXTET 10K 20-TSSOP |
| MAX5421AEUB+ | IC VOLTAGE DIVIDER DGLT 10MSOP |
| MS3450W22-4S | CONN RCPT 4POS WALL MNT W/SCKT |
| MAX5431AEUB+ | IC VOLTAGE DIVIDER PGA 10-UMAX |
| M83723/78W14048 | CONN PLUG 4POS STRAIGHT W/PINS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS1674J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Clock Driver |
| DS1674J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Clock Driver |
| DS1675 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| DS1675J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Memory Driver |
| DS1675J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Memory Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復。