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參數(shù)資料
| 型號： | DS1673S-5+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR SYSTEM PORT 5V 20-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 類型： | 便攜系統(tǒng)控制器 |
| 特點： | 警報器，閏年，監(jiān)視計時器 |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 3 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1673
6 of 18
TIME OF DAY ALARM BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS
MINUTES
HOURS
DAYS
DESCRIPTION
1
Alarm once per second.
0
1
Alarm when seconds match.
0
1
Alarm when minutes and seconds match.
0
1
Alarm when hours, minutes and seconds match.
0
Alarm when day, hours, minutes and seconds
match.
SPECIAL PURPOSE REGISTERS
The DS1673 has two additional registers (control register and status register) that control the RTC and
interrupts.
CONTROL REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
WP
AIS1
AIS0
0
AIE
EOSC
(Enable Oscillator). This bit, when set to logic 0 will start the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1673 is placed into a low-power standby mode with a current
drain of less than 200nA when in battery-backup mode. When the DS1673 is powered by VCC, the
oscillator is always on regardless of the status of the EOSC bit; however, the RTC is incremented only
when EOSC is a logic 0.
WP (Write Protect). Before any write operation to the RTC or any other registers, this bit must be logic
0. When high, the write protect bit prevents a write operation to any register.
AIS0-AIS1 (Analog Input Select). These 2 bits are used to determine the analog input for the analog-to-
digital conversion. Table 2 lists the specific analog input that is selected by these 2 bits.
AIE (Alarm Interrupt Enable). When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF)
bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the
INT signal.
ANALOG INPUT SELECTION Table 2
AIS1
AIS0
ANALOG INPUT
0
NONE
0
1
AIN0
1
0
AIN1
1
AIN2
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