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參數(shù)資料
| 型號： | DS1672-3 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 181K |
| 代理商： | DS1672-3 |
DS1672
6 of 12
DS1672 PROGRAMMABLE TRICKLE CHARGER
Figure 3
2-WIRE SERIAL DATA BUS
The DS1672 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1672 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (See Figure 4):
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy:
Both data and clock lines remain HIGH.
Start data transfer:
A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer:
A change in the state of the data line from low to high, while the clock line is high,
defines a STOP condition.
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES
1 OF 2
SELECT
1 OF 3
SELECT
TCS
BIT 7
TCS
BIT 6
TCS
BIT 5
TCS
BIT 4
DS
DS
RS
RS
BIT 3
BIT 2
BIT 1
BIT 0
250
R1
R2
TRICKLE CHARGE REGISTER
TCS = TRICKLE CHARGER SELECT
DS = DIODE SELECT
RS = RESISTOR SELECT
V
CC
V
BACKUP
2k
R3
4k
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