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參數(shù)資料
| 型號： | DS1672-3 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 181K |
| 代理商： | DS1672-3 |
DS1672
4 of 12
DS1672 REGISTERS
Figure 2
Address
B7
00h
B6
B5
B4
B3
B2
B1
B0
LSB
Function
Counter
Byte 1
Counter
Byte 2
Counter
Byte 3
Counter
Byte 4
Control
Trickle
Charger
01h
02h
03h
MSB
04h
05h
EOSC
TCS
TCS
TCS
TCS
DS
DS
RS
RS
DATA RETENTION MODE
The device is fully accessible and data can be written and ready only when V
CC
is greater than V
PF
.
However, when V
CC
falls below V
PF
, (point at which write protection occurs) the internal clock registers
are blocked from any access. If V
PF
is less than V
BACKUP
, the device power is switched from V
CC
to
V
BACKUP
when V
CC
drops below V
PF
. If V
PF
is greater than V
BACKUP
, the device power is switched from
V
CC
to V
BACKUP
when V
CC
drops below V
BACKUP
. The registers are maintained from the V
BACKUP
source
until V
CC
is returned to nominal levels.
OSCILLATOR CONTROL
The
EOSC
bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when
set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is placed into a low-power standby mode (I
BACKUP
) when in back-up mode. When the DS1672 is
powered by V
CC,
the oscillator is always on regardless of the status of the
EOSC
bit; however, the counter
is incremented only when
EOSC
is a logic 0.
MICROPROCESSOR MONITOR
A temperature-compensated comparator circuit monitors the level of V
CC
. When V
CC
falls to the power-
fail trip point, the
RST
signal (open drain) is pulled active. When V
CC
returns to nominal levels, the
RST
signal is kept in the active state for 250ms (typically) to allow the power supply and microprocessor to
stabilize. Note, however, that if the
EOSC
bit is set to a logic 1 (to disable the oscillator during write
protection), the reset signal will be kept in an active state for 250ms plus the start-up time of the
oscillator.
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