參數(shù)資料
型號(hào)： DS1629S+T&R
廠商： Maxim Integrated
文件頁(yè)數(shù)： 12/23頁(yè)
文件大小： 490K
描述： IC THERM/RTC/CALENDAR DIG 8-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
功能： 溫度計(jì)，恒溫計(jì)
傳感器類(lèi)型： 內(nèi)部
感應(yīng)溫度： -55°C ~ 125°C
精確度： ±2°C（最小值）
拓?fù)洌?/td> ADC，比較器，振蕩器，寄存器庫(kù)
輸出類(lèi)型： I²C?/SMBus?
輸出警報(bào)： 是
輸出風(fēng)扇： 無(wú)
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -55°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
DS1629
 
12 of 23
 
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the 
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
 
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the master to generate the STOP condition.
 
Figure 6 details how data transfer is accomplished on the two-wire bus. Depending upon the state of the
R/
 bit, two types of data transfer are possible:
 
1.
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the 
master is the slave address. Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
 
2.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) 
is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of
data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all
received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is
returned.
 
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
 
The DS1629 may operate in the following two modes:
 
1.
Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte 
is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after
reception of the slave address and direction bit.
 
2.
Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. 
However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1629 while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning and end of a serial transfer.
 
SLAVE ADDRESS
A control byte is the first byte received following the START condition from the master device. The
control byte consists of a 4-bit control code; for the DS1629, this is set as 1001 binary for read and write
operations. The next 3 bits of the control byte are the device select bits (A2, A1, A0). All 3 bits are hard-
wired high for the DS1629. Thus, only one DS1629 can reside on a 2-wire bus to avoid contention;
however, as many as seven other devices with the 1001 control code can be dropped on the 2-wire bus so
long as none contain the 111 address. The last bit of the control byte (R/
) defines the operation to be
performed. When set to a 1 a read operation is selected, and when set to a 0 a write operation is selected.
Following the START condition, the DS1629 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the control byte, the slave device outputs an ACK on the SDA line.
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