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參數(shù)資料
| 型號： | DS1629S+T&R |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 490K |
| 描述： | IC THERM/RTC/CALENDAR DIG 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 功能： | 溫度計，恒溫計 |
| 傳感器類型： | 內部 |
| 感應溫度： | -55°C ~ 125°C |
| 精確度： | ±2°C（最小值） |
| 拓撲： | ADC，比較器，振蕩器，寄存器庫 |
| 輸出類型： | I²C?/SMBus? |
| 輸出警報： | 是 |
| 輸出風扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
DS1629
11 of 23
CAL = Clock Alarm Latch. This volatile status bit will be set to 1 when the clock comparator becomes
active. Once set, it will remain latched until DS1629 power is cycled. A 0 in this location indicates the
clock has never been in an alarm condition since the DS1629 was powered-up. This is a read-only bit
(writes to this location constitute a dont care) and the power-up default is the flag cleared (CAL = 0).
TAL = Thermal Alarm Latch. This volatile status bit will be set to 1 when the thermal comparator
becomes active. Once set, it will remain latched until DS1629 power is cycled. A 0 in this location
indicates the DS1629 temperature has never exceeded T
H
since power-up. This is a read-only bit (writes
to this location constitute a dont care) and the power-up default is the flag cleared (TAL = 0).
0 = Dont care. Dont care on a write, but will always read out as a 0.
2-WIRE SERIAL DATA BUS
The DS1629 supports a bidirectional two-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that
controls the message is called a master. The devices that are controlled by the master are slaves. The
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1629 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined:
" Data transfer may be initiated only when the bus is not busy.
" During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data line, from high to low, while the clock is high,
defines a START condition.
Stop data transfer: A change in the state of the data line, from low to high, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th
bit.
The maximum clock rate of the DS1629 is 400kHz.
相關PDF資料 |
PDF描述 |
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| DS1631S+T&R | IC THERMOMETER DIG HI-PREC 8SOIC |
| DS1721U+T&R | IC THERMOMETER/STAT DIG HP 8USOP |
| DS1722S | IC THERMOMETER DIG 3-WIRE 8-SOIC |
| DS1775R7+T&R | IC THERMOM/STAT DIG 111 SOT-23-5 |
| DS1821C+ | IC THERMOMETER/STAT PROG 3-TO92 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1630AB-100-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1630AB-120-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1630AB-70-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1630AB-85-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1630ABL-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
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