參數(shù)資料
型號: DS1501Y
英文描述: Real-Time Clock
中文描述: 實(shí)時時鐘
文件頁數(shù): 11/30頁
文件大?。?/td> 291K
代理商: DS1501Y
DS1501/DS1511
11 of 30
The watchdog timer is reloaded when the processor performs a write of the Watchdog registers. The
time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to both
watchdog registers. The watchdog function is automatically disabled upon power-up by the POWER on
RESET setting WDE=0 and WDS=0. The watchdog registers are not initialized at power up and should
be initialized by the user.
The following summarizes the configurations in which the watchdog can be used.
1.
WDE=0 and WDS=0:
WDF will be set.
2.
WDE=0 and WDS=1:
WDF will be set.
3.
WDE=1 and WDS=0:
WDF and IRQF will be set, and the
IRQ
pin will be pulled low.
4.
WDE=1 and WDS=1:
WDF will be set, the
RST
pin will be pulled low for a duration of 40 ms to
200 ms, and ‘WDE’ will be reset to ‘0’.
CLEARING IRQ AND FLAGS
The Time of Day/Date Alarm Flag (TDF), Watchdog Flag (WDF), and Interrupt Request Flag (IRQF),
are cleared by reading the flag register (0EH) as shown in Figures 2a, 2b, and 2c. The address must be
stable for a minimum of 15 ns (t
IRQZ
). After the tIRQZ requirement has been met, either a change in
address (figure 2a), a rising edge of
OE
(figure 2b), or a rising edge of
CS
(Figure 2c) will cause the flags
to be cleared. The
IRQ
pin will go inactive after the IRQF flag is cleared.
IRQ AND FLAG WAVEFORMS (ADDRESS RELATED)
Figure 2a
相關(guān)PDF資料
PDF描述
DS1501YE Real-Time Clock
DS1501YS Real-Time Clock
DS1501 Y2K-Compliant Watchdog Real-Time Clocks
DS1511 Y2K-Compliant Watchdog Real-Time Clocks
DS1501-DS1511 Y2K-Compliant Watchdog Real-Time Clocks
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