參數(shù)資料
型號(hào): DS1500YN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 9/20頁(yè)
文件大小: 0K
描述: IC RTC Y2KC W/NV CTRL 5V 32-DIP
標(biāo)準(zhǔn)包裝: 13
類(lèi)型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,NVSRAM,方波輸出,監(jiān)視計(jì)時(shí)器,Y2K
存儲(chǔ)容量: 256B
時(shí)間格式: HH:MM:SS(24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 通孔
封裝/外殼: 32-DIP 模塊(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 32-EDIP
包裝: 管件
DS1500 Y2K Watchdog RTC with Nonvolatile Control
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regardless of the state of the watchdog enable (WDE) bit, to serve as an indication to the processor that a
watchdog timeout has occurred. The watchdog timer operates in two modes, repetitive and single-shot.
If WDE is 1 and the watchdog steering bit (WDS) is 0, the watchdog is in repetitive mode. When the watchdog
times out, both WDF and IRQF are set. IRQ goes active and IRQF goes to 1. The watchdog timer is reloaded when
the processor performs a write of the watchdog registers and the timeout period restarts. Reading the control A
register clears the IRQ flag.
If WDE and WDS are 1, the watchdog is in single-shot mode. When the watchdog times out, RST goes active for a
period of tREC. When RST goes inactive, WDE resets to 0. Writing a value of 00h to both watchdog registers
disables the watchdog timer. The watchdog function is automatically disabled upon power-up by the power-on
reset setting WDE = 0 and WDS = 0. The watchdog registers are not initialized at power-up and should be
initialized by the user.
Note: The TE bit must be used to disable transfers when writing to the watchdog registers.
The following summarizes the configurations in which the watchdog can be used:
WDE = 0 and WDS = 0: WDF is set.
WDE = 0 and WDS = 1: WDF is set.
WDE = 1 and WDS = 0: WDF and IRQF are set, and the IRQ pin is pulled low.
WDE = 1 and WDS = 1: WDF is set, the RST pin pulses low, and WDE resets to 0.
WAKEUP/KICKSTART
The DS1500 incorporates a wakeup feature, which powers on at a predetermined date by activating the PWR
output pin. In addition, the kickstart feature allows the system to be powered up in response to a low-going
transition on the KS pin, without operating voltage applied to the VCCI pin. As a result, system power can be applied
upon such events as key closure, or a modem-ring-detects signal. To use either the wakeup or the kickstart
features, the DS1500 must have an auxiliary battery connected to the VBAUX pin, and the oscillator must be running.
The wakeup feature is controlled through the time-of-day/date power-enable bit (TPE). Setting TPE to 1 enables
the wakeup feature. Transfers (TE) must be enabled for a wake up event to occur. Writing TPE to 0 disables the
wakeup feature. Similarly, the kickstart feature is controlled through the kickstart interrupt-enable bit (KIE).
If the wakeup feature is enabled, while the system is powered down (no VCCI voltage), the clock/calendar monitors
the current day or date for a match condition with day/date alarm register (0Bh). With the day/date alarm register,
the hours, minutes, and seconds alarm bytes in the clock/calendar register map (02h, 01h, and 00h) are also
monitored. As a result, a wakeup occurs at the day or date and time specified by the day/date, hours, minutes, and
seconds alarm register values. This additional alarm occurs regardless of the programming of the TIE bit. When the
match condition occurs, the PWR pin is automatically driven low. This output can turn on the main system power
supply, which provides VCCI voltage to the DS1500 as well as the other major components in the system. Also, at
this time, the time-of-day/date alarm flag is set, indicating that a wakeup condition has occurred.
If VBAUX is present, while VCC is low, the KS input pin is monitored for a low-going transition of minimum pulse width
tKSPW. When such a transition is detected, the PWR line is pulled low, as it is for a wakeup condition. Also at this
time, KSF is set, indicating that a kickstart condition has occurred. The KS input pin is always enabled and must be
held at a valid logic level.
The timing associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram.
The occurrence of either a kickstart or wakeup condition causes the PWR pin to be driven low, as described above.
During Interval 1, if the supply voltage on the VCCI pin rises above the greater of VBAT or VPF before the power-on
timeout period (tPOTO) expires, then PWR remains at the active-low level. If VCCI does not rise above the greater of
VBAT or VPF in this time, then the PWR output pin is turned off and returns to its high-impedance level. In this event,
the IRQ pin also remains tri-stated. The interrupt flag bit (either TDF or KSF) associated with the attempted power-
on sequence remains set until cleared by software during a subsequent system power-on.
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