I2C Digital Input RTC with Alarm ________________________________________" />
參數(shù)資料
型號(hào): DS1375T+
廠商: Maxim Integrated Products
文件頁數(shù): 7/13頁
文件大?。?/td> 0K
描述: IC RTC SERIAL W/ALARM 6-TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 100
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,方波輸出,涓流充電器
存儲(chǔ)容量: 16B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 1.7 V ~ 5.5 V
電壓 - 電源,電池: 1.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 6-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 6-TDFN 裸露焊盤(3x3)
包裝: 管件
產(chǎn)品目錄頁面: 1434 (CN2011-ZH PDF)
DS1375
I2C Digital Input RTC with Alarm
_____________________________________________________________________
3
Note 8:
After this period, the first clock pulse is generated.
Note 9:
A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 10:
The maximum tHD:DAT is only met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 11:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
≥ 250ns must then be met.
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250
= 1250ns before the SCL line is released.
Note 12:
CB—total capacitance of one bus line in pF.
AC ELECTRICAL CHARACTERISTICS
(VCC = VCCMIN to VCCMAX, TA = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
100
400
SCL Clock Frequency
fSCL
Standard mode
0
100
kHz
Fast mode
1.3
Bus Free Time Between STOP
and START Conditions
tBUF
Standard mode
4.7
s
Fast mode
0.6
Hold Time (Repeated) START
Condition (Note 8)
tHD:STA
Standard mode
4.0
s
Fast mode
1.3
Low Period of SCL Clock
tLOW
Standard mode
4.7
s
Fast mode
0.6
High Period of SCL Clock
tHIGH
Standard mode
4.0
s
Fast mode
0
0.9
Data Hold Time (Notes 9, 10)
tHD:DAT
Standard mode
0
0.9
s
Fast mode
100
Data Setup Time (Note 11)
tSU:DAT
Standard mode
250
ns
Fast mode
0.6
Start Setup Time
tSU:STA
Standard mode
4.7
s
Fast mode
300
Rise Time of Both SDA and SCL
Signals (Note 12)
tR
Standard mode
20 + 0.1CB
1000
ns
Fast mode
300
Fall Time of Both SDA and SCL
Signals (Note 12)
tF
Standard mode
20 + 0.1CB
300
ns
Fast mode
0.6
Setup Time for STOP Condition
tSU:STO
Standard mode
4.7
s
Capacitive Load for Each Bus
Line (Note 12)
CB
400
pF
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
tSP
Fast mode
30
ns
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