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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | DS1374C-18# |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 14/18闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RTC I2C W/CHARGER 16-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 椤炲瀷锛� | 浜岄€�(j矛n)鍒惰▓(j矛)鏁�(sh霉)鍣� |
| 鐗归粸(di菐n)锛� | 璀﹀牨(b脿o)鍣紝鏂规尝杓稿嚭锛屾稉娴佸厖闆诲櫒锛岀洠(ji膩n)瑕栬▓(j矛)鏅�(sh铆)鍣� |
| 鏅�(sh铆)闁撴牸寮忥細 | 浜岄€�(j矛n)鍒� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | 浜岄€�(j矛n)鍒� |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 1.71 V ~ 1.89 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 1.3 V ~ 3.7 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 绠′欢 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)鐣�(d膩ng)鍓嶇14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
_____________________________________________________________________
5
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40掳C to +85掳C) (Figure 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Detect to Recognize Inputs
(VCC Rising)
tRPU
(Note 24)
250
ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tF
300
渭s
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tR
0
渭s
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection.
Note 2:
Limits at -40掳C are guaranteed by design and not production tested.
Note 3:
All voltages are referenced to ground.
Note 4:
VBACKUP should not exceed VCC MAX or 3.7V, whichever is greater.
Note 5:
The use of the 250
惟 trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.
Note 6:
Measured at VCC = typ, VBACKUP = 0V, register 09h = A5h.
Note 7:
Measured at VCC = typ, VBACKUP = 0V, register 09h = A6h.
Note 8:
Measured at VCC = typ, VBACKUP = 0V, register 09h = A7h.
Note 9:
SCL only.
Note 10: SDA and SQW and INT.
Note 11: The RST pin has an internal 50k
惟 pullup resistor to VCC.
Note 12: Trickle charger disabled.
Note 13: ICCA鈥擲CL clocking at max frequency = 400kHz.
Note 14: Specified with I2C bus inactive.
Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 16: WDSTR = 1. BBSQW = 1 is required for operation when VCC is below the power-fail trip point (or absent).
Note 17: CB鈥攖otal capacitance of one bus line in pF.
Note 18: After this period, the first clock pulse is generated.
Note 19: The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIHMIN of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 21: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
鈮� to 250ns must be met. This is
automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before
the SCL line is released.
Note 22: Guaranteed by design. Not production tested.
Note 23: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V
鈮� VCC 鈮� VCC MAX and 1.3V 鈮� VBACKUP 鈮� 3.7V.
Note 24: This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is
added to this delay.
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| DS1374C-18# | 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� I2C 32-Bit Binary Counter Watchdog RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS1374C-3 | 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� I2C 32-Bit Binary Counter Watchdog RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS1374C-3- | 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output |
| DS1374C-3# | 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� I2C 32-Bit Binary Counter Watchdog RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS1374C-3#T&R | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:2-WIRE ETC W/CRYSTAL 3V ROHS T/R - Tape and Reel 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:IC RTC I2C 32BIT 3.0V 16-SOIC 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:Real Time Clock I2C 32-Bit Binary Counter Watchdog |
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