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參數(shù)資料
| 型號(hào)： | DS1350Y |
| 元件分類： | DRAM |
| 英文描述： | 4096k Nonvolatile SRAM with Battery Monitor |
| 中文描述： | 4096k非易失SRAM，帶有電池監(jiān)視器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 228K |
| 代理商： | DS1350Y |
DS1350Y/AB
8 of 12
POWER-DOWN/POWER-UP TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
V
CC
slew from V
TP
to 0V
t
F
V
CC
Fail Detect to
RST
Active
t
RPD
V
CC
slew from 0V to V
TP
t
R
V
CC
Valid to
CE
and
WE
Inactive
t
PU
V
CC
Valid to End of Write Protection
t
REC
V
CC
Valid to
RST
Inactive
t
RPU
V
CC
Valid to
BW
Valid
t
BPU
MIN
TYP
MAX
1.5
UNITS
μ
s
μ
s
μ
s
μ
s
ms
ms
ms
s
NOTES
11
150
15
14
150
2
125
350
1
150
200
14
14
BATTERY WARNING TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
Battery Test Cycle
t
BTC
Battery Test Pulse Width
t
BTPW
Battery Test to
BW
Active
t
BW
MIN
TYP
24
MAX
UNITS
hr
s
s
NOTES
1
1
(t
A
=25
°
C)
PARAMETER
SYMBOL
Expected Data Retention Time
t
DR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high-impedance state.
3.
t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4.
t
DS
are measured from the earlier of
CE
or
WE
going high.
5.
These parameters are sampled with a 5 pF load and are not 100% tested.
6.
If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output
buffers remain in a high-impedance state during this period.
7.
If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high-impedance state during this period.
8.
If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high-impedance state during this period.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1350BL-100-IND | NVRAM (Battery Based) |
| DS1350BL-70 | NVRAM (Battery Based) |
| DS1350BL-70-IND | NVRAM (Battery Based) |
| DS1350WP-150 | NVRAM (Battery Based) |
| DS1350YL-100 | NVRAM (Battery Based) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1350Y/AB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350Y-70 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350YL-100 | 功能描述:IC NVSRAM 4MBIT 100NS 34LPM RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
| DS1350YL-100-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1350YL-70 | 功能描述:IC NVSRAM 4MBIT 70NS 34LPM RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
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