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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DS1338C-18# |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/16闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC RTC 56BIT NV SRAM 16-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 椤炲瀷锛� | 鏅傞悩/鏃ユ |
| 鐗归粸锛� | 闁忓勾锛孨VSRAM锛屾柟娉㈣几鍑� |
| 瀛樺劜瀹归噺锛� | 56B |
| 鏅傞枔鏍煎紡锛� | HH:MM:SS锛�12/24 灏忔檪锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 1.71 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 1.3 V ~ 3.7 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 绠′欢 |
DS1338 I2C RTC with 56-Byte NV RAM
12 of 16
I2C SERIAL DATA BUS
The DS1338 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data is a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device, which generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1338
operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate)
and a fast mode (400kHz maximum clock rate) are defined. The DS1338 works in both modes. Connections to the
bus are made through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 5).
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines
the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception
of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP condition.
Figure 5. Data Transfer on I2C Serial Bus
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| DS1673S-5+T&R | IC CTRLR SYSTEM PORT 5V 20-SOIC |
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| MAX5421AEUB+ | IC VOLTAGE DIVIDER DGLT 10MSOP |
| MS3450W22-4S | CONN RCPT 4POS WALL MNT W/SCKT |
| MAX5431AEUB+ | IC VOLTAGE DIVIDER PGA 10-UMAX |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS1338C-18# | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 I2C Serial RTC w/56 Byte NV RAM RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS1338C-18+ | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:REAL TIME CLOCK SERL 56BYTE 16SOIC - Bulk |
| DS1338C-3 | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS1338C-3# | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 I2C Serial RTC w/56 Byte NV RAM RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS1338C-3+ | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:REAL TIME CLOCK SERL 56BYTE 16SOIC - Bulk |
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