參數(shù)資料
型號(hào): DS1337S
英文描述: Serial Real-Time Clock
中文描述: 串行實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù): 7/13頁(yè)
文件大?。?/td> 364K
代理商: DS1337S
DS1337
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit
noise coupled into the oscillator circuit can result in the clock running fast. Refer to
Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks
for detailed information.
ADDRESS MAP
The address map for the registers of the DS1337 is shown in Table 1. During a multibyte access, when
the address pointer reaches the end of the register space (0Fh) it wraps around to location 00h. On a 2-
wire START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a
second set of registers. The time information is read from these secondary registers, while the clock may
continue to run. This eliminates the need to re-read the registers in case of an update of the main registers
during a read.
Table 1. Timekeeper Registers
7 of 13
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
00H
01H
0
0
10 Seconds
10 Minutes
AM/PM
Seconds
Minutes
Seconds
Minutes
00-59
00-59
1-12
+AM/PM
00-23
1-7
00-31
01-12 +
Century
00-99
02H
0
12/24
10hr
10hr
Hour
Hours
03H
04H
0
0
0
0
0
0
0
Day
Day
Date
Month/
Century
Year
10 Date
Date
05H
Century
0
0
10 Mo
Month
06H
10 Year
Year
07H
A1M1
10 Seconds
Seconds
Alarm 1
Seconds
00-59
08H
A1M2
10 Minutes
Minutes
Alarm 1
Minutes
00-59
AM/PM
09H
A1M3
12/24
10hr
10hr
Hour
Alarm 1
Hours
1-12 +
AM/PM
00-23
0AH
A1M4
DY/DT
10 DATE
Day
Date
Alarm 1
Day
Alarm 1
Date
Alarm 2
Minutes
1-7
1-31
0BH
A2M2
10 Minutes
Minutes
00-59
AM/PM
0CH
A2M3
12/24
10hr
10hr
Hour
Alarm 2
Hours
1-12 +
AM/PM
00-23
0DH
A2M4
DY/DT
10 Date
Day
Date
Alarm 2
Day
Alarm 2
Date
Control
Status
1-7
1-31
0EH
0FH
EOSC
OSF
0
0
0
0
RS2
0
RS1
0
INTCN
0
A2IE
A2F
A1IE
A1F
Note:
Unless otherwise specified, the state of the registers is not defined when power is first applied or V
CC
falls below the V
OSC
.
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