參數(shù)資料
型號(hào): DS1337S
英文描述: Serial Real-Time Clock
中文描述: 串行實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù): 3/13頁(yè)
文件大小: 364K
代理商: DS1337S
DS1337
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 1.8V to 4.0V, T
A
= -40°C to +85°C.)
PARAMETER
3 of 13
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
Standard mode
Fast mode
100
1.3
400
100
SCL Clock Frequency
f
SCL
kHz
Bus Free Time Between a
STOP and START Condition
t
BUF
Standard mode
4.7
s
Fast mode
0.6
Hold Time (Repeated)
START Condition (Note 8)
t
HD:STA
Standard mode
4.0
s
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
LOW Period of SCL Clock
t
LOW
s
HIGH Period of SCL Clock
t
HIGH
s
Setup Time for a Repeated
START Condition
t
SU:STA
s
0.9
300
Data Hold Time (Notes 9, 10)
t
HD:DAT
s
Data Setup Time (Note 11)
t
SU:DAT
ns
20 + 0.1C
B
Rise Time of Both SDA and
SCL Signals (Note 12)
t
R
Standard mode
1000
ns
Fast mode
20 + 0.1C
B
300
Fall Time of Both SDA and
SCL Signals (Note 12)
t
F
Standard mode
Fast mode
Standard mode
300
ns
0.6
4.0
Setup Time for STOP
Condition
Capacitive Load for Each Bus
Line
t
SU:STO
s
C
B
(Note 12)
400
pF
I/O Capacitance
C
I/O
10
pF
Note 1:
SCL only.
Note 2:
SDA,
INTA
, and SQW/
INTB
.
Note 3:
I
CCA
—SCL clocking at max frequency = 400kHz, V
IL
= 0.0V, V
IH
= V
CC.
Note 4:
Specified with 2-wire bus inactive, V
IL
= 0.0V, V
IH
= V
CC.
Note 5:
SQW enabled.
Note 6:
Specified with the SQW function disabled by setting INTCN = 1.
Note 7:
Using recommended crystal on X1 and X2.
Note 8:
After this period, the first clock pulse is generated.
Note 9
: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
Note 10
: The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 11:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
to 250ns must then be met. This is
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R max
+
t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is
released.
Note 12:
C
B
—total capacitance of one bus line in pF.
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